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Hard fault on unaligned access on STM32U5

Meixner
Associate II

Hello,

 

I have a problem with unaligned access, which generates a hard fault when the software is started without bootloader.

When running the same software from mcuboot bootloader, there is no hard fault on unaligned access.

The MPU and TrustZone configuration is the same in both cases.

So I know that CM33 in STM32U5 supports unaligned memory access, since it is working when started from the bootloader. Now the question is, what is the difference? What do I need to do to enable unaligned memory access?

SCB->CCR is already set to not trigger faults on unaligned access.

The access should go to address 0x30000d8d

SCB settings:

CPUID = 0x410fd214,
ICSR = 0x456803,
VTOR = 0xc000000,
AIRCR = 0xfa050300,
SCR = 0x0,
CCR = 0x201,
SHPR = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf0, 0x0},
SHCSR = 0x80004,
CFSR = 0x1000000,
HFSR = 0x40000000,
DFSR = 0x1,
MMFAR = 0x30018e1c,
BFAR = 0x30018e1c,
AFSR = 0x0,
ID_PFR = {0x30, 0x210},
ID_DFR = 0x200000,
ID_AFR = 0x0,
ID_MMFR = {0x101f40, 0x0, 0x1000000, 0x0},
ID_ISAR = {0x1101110, 0x2212000, 0x20232232, 0x1111131, 0x1310132, 0x0},
CLIDR = 0x0,
CTR = 0x8000c000,
CCSIDR = 0x0,
CSSELR = 0x0,
CPACR = 0xf00000,
NSACR = 0xc00,
SFSR = 0x0,
SFAR = 0x30018e1c,
STIR = 0x0,
MVFR0 = 0x10110021,
MVFR1 = 0x11000011,
MVFR2 = 0x40,
ICIALLU = 0x0,
ICIMVAU = 0x0,
DCIMVAC = 0x0,
DCISW = 0x0,
DCCMVAU = 0x0,
DCCMVAC = 0x0,
DCCSW = 0x0,
DCCIMVAC = 0x0,
DCCISW = 0x0,
BPIALL = 0x0

1 ACCEPTED SOLUTION

Accepted Solutions
Meixner
Associate II

I have found the issue: MAIR configuration was written to MAIR1 instead of MAIR0.

View solution in original post

1 REPLY 1
Meixner
Associate II

I have found the issue: MAIR configuration was written to MAIR1 instead of MAIR0.