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FAQ: Error flashing Zephyr firmware with STLINK-V3MINI (SWD) by openocd runner in steval_stwinkt1 dev kit.

RArte.1
Associate II

I tried to flash Zephyr Firmware by DFU and I the firmware flashed as I expected.

0693W00000bhHOTQA2.pngIn the other hand, I tried flashing firmware by STLINK-V3MINI something raise an error.

0693W00000bhHQQQA2.pngThis is the contents of board.cmake file:

# west flash -r openocd
 
# west flash -r dfu-util
 
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
 
board_runner_args(jlink "--device=STM32L4R9ZIJ6" "--speed=4000")
 
board_runner_args(pyocd "--target=STM32L4")
 
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
 
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
 
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)

Also, this is the contents of openocd.cfg file:

# source [find interface/stlink.cfg]
 
source [find interface/stlink-dap.cfg]
 
set WORKAREASIZE 0x8000
 
# transport select hla_swd
 
# Transport SWD protocol
 
transport select "dapdirect_swd"
 
set CHIPNAME STM32L4R9ZIJx
 
set BOARDNAME STEVAL-STWINKT1
 
# Enable debug when in low power mode
set ENABLE_LOW_POWER 1
 
# Stop watchdog counter when halt
set STOP_WATCHDOG 1
 
# STlink debug clock frequency
set CLOCK_FREQ 4000
 
# Reset configuration
# Use hardware reset, connect under reset
# connect_assert_srst nedded if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
 
source [find target/stm32l4x.cfg]
 
# $_TARGETNAME configure -event gdb-attach {
#   echo "Debugger attaching: halting execution"
#   reset halt
#   gdb_breakpoint_override hard
# }
 
# $_TARGETNAME configure -event gdb-detach {
#   echo "Debugger detaching: resuming execution"
#   resume
# }

Thanks!

1 ACCEPTED SOLUTION

Accepted Solutions
RArte.1
Associate II

The issue was that in the openocd.cdg file I was written:

source [find target/stm32f4x.cfg] in state of source [find target/stm32l4x.cfg]

So the issue was fixed 😅

View solution in original post

1 REPLY 1
RArte.1
Associate II

The issue was that in the openocd.cdg file I was written:

source [find target/stm32f4x.cfg] in state of source [find target/stm32l4x.cfg]

So the issue was fixed 😅