f_write returns FR_DISK_ERR when trying to write large chunks

[Podkovirin.Anton]

Posted on December 28, 2017 at 17:29

I'm working with the F7 microcontroller and MXCube v1.8.0 for the uC peripherals configuration. The sdcard interface is configured to use DMA for the RX and TX operations.

I can successfully open/close/read files, but when trying to write large chunks, i get into some issues.

I open the file with the rewrite flag.

The data that needs to be written is stored in the SDRAM, so i just send a pointer to the beginning of the data in the SDRAM, and the size (about 970KB) to the f_write function.

After a random amount of written data (can be 2KB and also 40KB), DMA transfer error is triggered, which results in the FR_DISK_ERR.

When updated the code to write the data in chunks of 512 bytes (loop of f_write with maximum size of 512), the full data is written successfully.

Any ideas what i am  doing wrong, or what might be the issue?

I did try the bug fixes for the FATFS, suggested here, but non of them solved the issue. 

#dma #fr_disk_err #fatfs #stm32f7

[con3]

Posted on January 29, 2018 at 19:41

Hey APod,  I seem to have the same issue. Were you able to figure out what the problem is? 

[Tesla DeLorean]

Posted on January 29, 2018 at 20:27

With DMA on the F7 you need to be cognoscente of the cache and coherency.

Not seeing FR_DISK_ERR on the F7, but generally writing large 512 byte aligned blocks, or order 32KB.

When doing unaligned work the driver is going to be reading and writing sectors to account for partial changes split across them.

I would advise using polled mode for single sector writes, it uses a different bounded command. I did this in the diskio.c layer. These writes are typically of the FAT itself and system structures, or buffer management within FatFS. Instrument the diskio.c layer via USART or SWV to understand the failure pattern, and how your writes have been decomposed and interleaved with file system structure writes.

Important also that you wait for the DMA callback, and then wait for the MMC completion, the latter occurring after the FIFOs have cleared the interface.