Posted on August 18, 2016 at 16:10The F4 has a FIFO buffer to reduce bus contention when DMA is active. The 4/8/16 ''beat'' is the number of bus transfers the DMA unit performs when it gains access to the AHB bus for a transfer. It corresponds to one, two or four accesses, aligned on a byte, half word or word boundary. By buffering the DMA unit avoids the overhead of arbitrating for bus access.
Consider a USART transmit of a long text string, say 128 bytes long. Single byte DMA would require 128 bus accesses to read data from memory and 128 accesses to write to the USART register. Now add in a basic 4 byte ''beat'', and the bus arbitration is reduced to 128/4 or 32 bursts. And if the data is word aligned, the unpack feature can read words from memory instead of bytes, so the 32 byte bursts are reduced to 8 word bursts. That reduces bus arbitration from 128 to 8 and read cycles from 128 to 32, a significant time saver. That arbitration time is recovered in faster access to data from SRAM, or more DMA cycles available for other peripherals.
It takes some work to optimize this but it's an important feature of the STM32 over some other vendors' CM4 products. While fetching instructions from flash the DMA transfers between SRAM and AHB/APB peripherals is essentially free since it occurs in parallel with instruction fetches. Where it becomes important is operating with high ADC conversion rates, where a lot of data has to be moved around. Parallel operations free up processing time in the CPU.
The FIFO thresholds are used when high data rates in DMA are required. As the FIFO buffer is emptied to a threshold a DMA interrupt is used to set up a new transfer to keep the FIFO full.
Using the FIFO is complicated, since the buffer alignment, count, pack/unpack and peripheral thruput all have to be balanced. But for certain applications it's invaluable.
Jack Peacock
