[CMSIS] Missing CSTF bit definition for ETH_MACCR register

[Piranha]

The CSTF bit definition for ETH_MACCR register is missing from all CMSIS header definition files for F7, F4 and F2 series MCUs with ETH peripheral. F1 series doesn't have this bit or at least it isn't documented in the reference manual. I guess for F1 it is not an error of the reference manual, SVD files and header files and the hardware actually doesn't have this feature?

This bit enables a feature, which strips CRC from the received frames by hardware. Probably because the definitions of this bit are missing, but most likely because the HAL developers do not read the documentation, the HAL code does not use this feature. Instead the HAL code subtracts the size of CRC manually. This is done in the HAL_ETH_ReadData() function for the newer rewritten drivers and HAL_ETH_GetReceivedFrame() and HAL_ETH_GetReceivedFrame_IT() for the older drivers. Of course, this is also true for F7, F4 and F2 series.

[KDJEM.1]

Hello @Piranha​,

Thank you for bringing this issue to our attention.

I confirm this issue for STM32F7, STM32F4 and STM32F2 series.

I reported internally.

Internal ticket number: 143308 (This is an internal tracking number and is not accessible or usable by customers).

Thanks for your contribution in STCommunity. 

Kaouthar