2024-12-05 09:49 AM
The net effect of this bug is that the reference code (including the Templates for LRUN and XIP) never actually enable the Memory Protection Unit regions.
See: stm32h7rsxx_hal_cortex.c Line 532
I believe the second "Disable the Region" should have been an "Enable the Region", and called SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk).
Without this, the result after a call to HAL_MPU_ConfigRegion is a disabled region, requiring a second call to HAL_MPU_EnableRegion(). Note that there are no calls to this function in the H7RS reference code or templates. As a result, these regions are never enabled.
I discovered this issue when a region I marked as non-cachable was being cached despite the region specifically declaring it as NOT_CACHABLE.
Solved! Go to Solution.
2024-12-05 09:57 AM
Please disregard. I missed that the bit is overridden in the RASR set below. The dual CLEAR_BIT is probably not necessary, but seemingly harmless.
Now to figure out why my noncacheable region is still being cached...
2024-12-05 09:57 AM
Please disregard. I missed that the bit is overridden in the RASR set below. The dual CLEAR_BIT is probably not necessary, but seemingly harmless.
Now to figure out why my noncacheable region is still being cached...