Bare metal USB HID

[Nickelgrass]

Hello,

I am trying to implement a USB HID keyboard on an STM32F042 without HAL or LL, just simple register defs. I took an example code generated in CubeIDE with HAL and a few other examples. I extended the example with HAL to also implement the LEDs which all works fine. 

I understand how it basically works. I define the descriptors and configure the Endpoints etc. Then I need to transfer the descriptors when the host requires them. But what I can not figure out is how exactly the descriptors are actually transferred. The HAL is so overloaded that it seems impossible to find the exact lines of code where the descriptors are transferred to the host and how that is done exactly. Also where do I put the report descriptor to send some key presses? Can anyone give me some info on how that is done?

[Nickelgrass]

Maybe someone from ST can point me to some additional documentation for the USB peripheral and the PMA?

[STOne-32]

Dear @Nickelgrass ,

Full description of USB and PMA SRAMs is here :https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf#page1262

Not  an easy task to handle , all the processing should be interrupt based .Let us know

Hope it helps you .

Ciao

STOne-32

 

[Nickelgrass]

Thanks for the reply. I read the RM (of F042). But I somewhat hoped there was a more detailed explanation to the PMA. Something like a concrete map of what goes where.

Is it correct that the PMA is 16 bit registers but 32 bit aligned?

So from the logic of how it works is that I get an interrupt. The host requests a specific descriptor. I load the descriptor in the PMA and then send it of. Is that basically how it works?

[STOne-32]

Hi @Nickelgrass,

Here is a legacy STM32F1 series library documentation which was the first software implementation before F0 series , there are some similarities.

https://www.st.com/resource/en/user_manual/um0424-stm32-usbfsdevice-development-kit-stmicroelectronics.pdf

PMA is a kind optimized dual port SRAM where the Core and USB are able to write and read , endpoints should be well programmed with the right size .

Hope it helps ,

STOne-32

[Nickelgrass]

Thanks! I had not found that yet.