Timer trigger GPDMA to GPIO without HAL

[beSTMax]

Hello,

I'm trying to port the example found here: https://blog.embeddedexpert.io/?p=1680 to NUCLEO-U385RG-Q.

The example in the link is for STM32F411. I've successfully tried the example.

Verbatim port of the code leads to USEF being set in GPDMA_C0SR.

There are some unclear things about GPDMA:

• Reading generated HAL code: when memory-to-peripheral is chosen, DREQ bit is set in GPDMA_CxTR2, otherwise, SWREQ is set. I can't make sense of this fact and documentation given in RM0487.
• To achieve circular mode (i.e. setting CIRC bit in DMA_SxCR for STM32F411) do I have to use linked-list mode?I can imagine a linked list of length one pointing back to itself. Or does it have to be linked list of length two (First element is for setting GPIO bit, second element is for resetting GPIO bit) ?

Thanks in advance

int main(void)
{

  /* USER CODE BEGIN 1 */

  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();

  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();

  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
  /* USER CODE BEGIN 2 */

  uint32_t set_reset[] = {
    GPIO_BSRR_BS5, GPIO_BSRR_BR5
  };

  SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN);

  MODIFY_REG(GPIOA->MODER, GPIO_MODER_MODE5, GPIO_MODER_MODE5_0);

  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN);

  SET_BIT(TIM2->DIER, TIM_DIER_UDE);

  TIM2->PSC = 16000-1;
  TIM2->ARR = 1000-1;

  SET_BIT(RCC->AHB1ENR1, RCC_AHB1ENR1_GPDMA1EN);

  SET_BIT(GPDMA1_Channel0->CCR, DMA_CCR_RESET);

  while (GPDMA1_Channel0->CCR & DMA_CCR_EN)
    ; // wait till disabled

  MODIFY_REG(GPDMA1_Channel0->CTR1, DMA_CTR1_DDW_LOG2, DMA_CTR1_DDW_LOG2_1);

  MODIFY_REG(GPDMA1_Channel0->CTR1, DMA_CTR1_SDW_LOG2, DMA_CTR1_SDW_LOG2_1);
  MODIFY_REG(GPDMA1_Channel0->CTR2, DMA_CTR2_REQSEL, 60);
  SET_BIT(GPDMA1_Channel0->CTR1, DMA_CTR1_SINC);

  MODIFY_REG(GPDMA1_Channel0->CBR1, DMA_CBR1_BNDT, 2);
  MODIFY_REG(GPDMA1_Channel0->CSAR, DMA_CSAR_SA, (uint32_t)set_reset);
  MODIFY_REG(GPDMA1_Channel0->CDAR, DMA_CDAR_DA, (uint32_t)&GPIOG->BSRR);

  SET_BIT(GPDMA1_Channel0->CCR, DMA_CCR_EN);

  SET_BIT(TIM2->CR1, TIM_CR1_CEN);

  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
    /* USER CODE END WHILE */

    /* USER CODE BEGIN 3 */
  }
  /* USER CODE END 3 */
}

EDIT: fixed request number

[genehill34]

I’ve found the RM0487 a bit opaque too when dealing with GPDMA. One tip — make sure the node data size and burst settings match your target peripheral’s expectation (even if it’s GPIO). Misalignments there often lead to USEF being set.

[beSTMax]

Hi!

Thank you very much for your input. I read the section in the reference manual again. Indeed, BNDT is the block number of data bytes. So for a word (uint32_t) I think that the block number of bytes is 4 (I'm still not entirely sure, how block and burst are related).

With that change, the LED is still not blinking, but there is no USEF anymore.

[KDJEM.1]

Hello @beSTMax;

The STM32F411 and the STM32U385 have different DMA architectures and features. You can check the differences under these application notes under "Direct memory access controller" section.

- Migrating from STM32F401 and STM32F411 lines to STM32L4 Series and STM32L4+ Series microcontrollers - Application note

- Migrating from STM32L4 and STM32L4+ to STM32U3 MCUs - Application note

For more information about the GPDMA , I recommend you to look at How to use the GPDMA for STM32 MCUs application note.

Thank you.

Kaouthar

[beSTMax]

Hello @KDJEM.1 ,

thanks for the links, esp. the migration guides.

I've read the AN5593 (skimmed at least). In 2.5 there is some definition of "burst", but that is explained with a "beat".

I must confess that I don't understand everything in there, but I'm aware that the two DMA implementations (for F4 and U3) differ.

The exercise is to better understand the workings of GPDMA.

Thanks!