STM32U5A9J-DK OctalFlash Read failure

[JKim.2]

Hello,

I generated a project for STM32U5A9J-DK with STM32CubeIDE (v1.16.0). It doesn’t include the OctalFlash test code. So, I used the test codes in chapter "Octo-SPI FLASH in Regular-command protocol example" of attached AN5050.

The mounted OctalFlash is MX25UM51245G. With the program, the data output was shifted by one byte as below.

After I use the HAL_OSPI_DELAY_BLOCK, the pass rate becomes higher but still fails. Please help.

Thanks.

• result from the default program w/o HAL_OSPI_DELAY_BLOCK

FAILURE index 0x00000000 Expect 0x20 Output 0x50

FAILURE index 0x00000001 Expect 0x50 Output 0x20

FAILURE index 0x00000002 Expect 0x72 Output 0x50

FAILURE index 0x00000003 Expect 0x6F Output 0x72

FAILURE index 0x00000004 Expect 0x67 Output 0x6F

FAILURE index 0x00000005 Expect 0x72 Output 0x67

FAILURE index 0x00000006 Expect 0x61 Output 0x72

FAILURE index 0x00000007 Expect 0x6D Output 0x61

SUCCESS index 0x00000008 Expect 0x6D Output 0x6D

FAILURE index 0x00000009 Expect 0x69 Output 0x6D

FAILURE index 0x0000000A Expect 0x6E Output 0x69

FAILURE index 0x0000000B Expect 0x67 Output 0x6E

• result from the modified program with HAL_OSPI_DELAY_BLOCK

• FAILURE index 0x00000000 Expect 0x20 Output 0x40

  SUCCESS index 0x00000001 Expect 0x50 Output 0x50

  FAILURE index 0x00000002 Expect 0x72 Output 0x50

  SUCCESS index 0x00000003 Expect 0x6F Output 0x6F

  FAILURE index 0x00000004 Expect 0x67 Output 0x6F

  SUCCESS index 0x00000005 Expect 0x72 Output 0x72

  SUCCESS index 0x00000006 Expect 0x61 Output 0x61

  SUCCESS index 0x00000007 Expect 0x6D Output 0x6D

  SUCCESS index 0x00000008 Expect 0x6D Output 0x6D

  SUCCESS index 0x00000009 Expect 0x69 Output 0x69

  FAILURE index 0x0000000A Expect 0x6E Output 0x68

  SUCCESS index 0x0000000B Expect 0x67 Output 0x67

[JKim.2]

Hi Kaouthar,

I removed all STM32U5 MCU packages and installed 1.6.0 again. The OSPI_NOR_MemoryMapped project still can't be compiled. Your suggestion for the .ioc file is only can be done on the original project. So, I changed the device size, SSHT disabled, DHQC enabled because the OCTAL_IO_DTR_READ_CMD(0xEE11) is used. The result is changed as below. The compressed project is attached.

Best Regards,

Jeff

FAILURE index 0x00000000 Expect 0x20 Output 0x50
FAILURE index 0x00000001 Expect 0x50 Output 0x20
FAILURE index 0x00000002 Expect 0x72 Output 0x50
FAILURE index 0x00000003 Expect 0x6F Output 0x72
FAILURE index 0x00000004 Expect 0x67 Output 0x6F
FAILURE index 0x00000005 Expect 0x72 Output 0x67
FAILURE index 0x00000006 Expect 0x61 Output 0x72
FAILURE index 0x00000007 Expect 0x6D Output 0x61
SUCCESS index 0x00000008 Expect 0x6D Output 0x6D
FAILURE index 0x00000009 Expect 0x69 Output 0x6D
FAILURE index 0x0000000A Expect 0x6E Output 0x69
FAILURE index 0x0000000B Expect 0x67 Output 0x6E

[KDJEM.1]

Hello @JKim.2 ,

Do you get the same behavior when using STR mode?

Thank you for sharing your project. For the first check, I noted the memory type is wrong. For DTR read the memory must be configured as "MACRONIX"  as mentioned in AN5050.

The memory type depends on the D0/D1 ordering: The micron (and compatible memories) use D0/D1 Ordering while Macronix (and compatible memories) use D1/D0 data ordering and Macronix RAM (and compatible memories)  use D1/D0 ordering with dedicated address mapping.

You can find in attached file an example describes how to erase a part of an OSPI NOR memory, write data in memory-mapped mode and access to OSPI NOR memory in STR memory-mapped mode using STM32U5A9J-DK discovery board. I hope this help you. 

Thank you.

Kaouthar

[JKim.2]

Hello Kaouthar,

Thank you for reviewing my project. Changing the memory type from MICRON to MACRONIX didn't change the result.

I tried your OSPI STR project. The case 1 includes write and read operation to OSPI device. However, CmdCplt stays at zero. So, the case 1 codes are skipped infinitely. What does this problem mean?

Best Regards,

Jeff

  while (1)
  {
	  switch(step)
	      {
	        case 0:
	          CmdCplt = 0;

	          /* Enable write operations ------------------------------------------ */
	          OSPI_WriteEnable(&hospi1);

	          /* Erasing Sequence ------------------------------------------------- */
	          sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
	          sCommand.Instruction   = OCTAL_SECTOR_ERASE_CMD;
	          sCommand.AddressMode   = HAL_OSPI_ADDRESS_8_LINES;
	          sCommand.Address       = address;
	          sCommand.DataMode      = HAL_OSPI_DATA_NONE;
	          sCommand.DummyCycles   = 0;

	          if (HAL_OSPI_Command_IT(&hospi1, &sCommand) != HAL_OK)
	          {
	            Error_Handler();
	          }

	          step++;
	          break;

	        case 1:
	          if(CmdCplt != 0)
	          {
	            CmdCplt = 0;

	            /* Configure automatic polling mode to wait for end of erase ------ */
	            OSPI_AutoPollingMemReady(&hospi1);

	            /* Enable write operations ---------------------------------------- */
	            OSPI_WriteEnable(&hospi1);

[KDJEM.1]

Hello @JKim.2 ,

Could you please place a breakpoint in main.c after HAL_OSPI_CmdCpltCallback function and click on resumeand check if CmdCplt change value or not?

void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi)
{
  CmdCplt++;
}

 On my side I see that the value of CmpCplt changes from 0 to 1 as shown in the below figures

To check the memory content, could you please set a break point after reading sequence. As shown in the below figure you can say the same content as in aTxBuffer[]

For the DTR read I find an example in STM32Cube_FW_U5_V1.6.0 \STM32Cube\Repository\STM32Cube_FW_U5_V1.6.0\Projects\STM32U575I-EV\Examples\DLYB\DLYB_OSPI_NOR_FastTuning

Please get inspired from this example to check your project precisely Dummy cycle and memory delay. 

Thank you.

Kaouthar

[JKim.2]

Hello Kaouthar,

CmdCplt value can be changed on HAL_OSPI_CmdCpltCallback function as below picture.

However, it becomes zero in the switch(step) loop when the step is 1. But sometimes CmdCplt becomes 1 when the step is 1. I don't know why the result is not consistent. Even when the step 1 code is executed, the printf doesn't print the flash memory data. Although I enabled UART by the pinout configuration like the old project, it seems UART is not working. The slightly modified OCTOSPI STR project is compressed and attached.

Best Regards,

Jeff

 

 

[KDJEM.1]

Hello @JKim.2 ,

After checking your project, I noted that you use a wrong USART.

Could you please try with USART1 pin PA9 and pin PA10 as shown in the below figure (UM2967)

This is a screenshot of terminal with matched index:

Thank you for your contribution in STCommunity.

Thanks and best regards,

Kaouthar

[KDJEM.1 · Accepted solution]

Hi @JKim.2 ,

For DTR read, I used the delay block in order to fine tune the data-received sampling clock. Also the delay block role is used to apply a phase-shift to the clock or DQS signal when reading from external memory. You can find in the attachment file a project with successful DTR OCTAL Read.

For more information for the delay block, I advise you to take a look at AN5050 Section 6 OCTOSPI and HSPI/XSPI interface calibration process.

Please let me know if your issue is solved or not?

Thank you.

Kaouthar

[JKim.2]

Hi Kaouthar,

Thank you so much for your help. Both STR and DTR project start working. 

However, it's hard to understand how it was solved just with reading the AN5050. 

Best Regards,

Jeff