Question about interfacing 4 I2S microphones with STM32F4

[Phung Tuan Hoang]

Hi I am designing a PCB for sampling 4 audio channels from 4 I2S MEMs microphone and doing some audio processing on it. My MCU STM32F407 has 5 I2S peripherals and I plan to use I2S2 and I2S3 for each pair of microphones. The configuration of each I2S is below (same for both):

My question is let's say I start I2S2 and I2S3 like following:

// 4000 samples (24 bits over 32-bit word)
uint32_t * first_buffer = malloc(4000 * sizeof(uint32_t));
uint32_t * second_buffer = malloc(4000 * sizeof(uint32_t));
 
// DMA transfer size is byte, hence * 4
HAL_I2S_Receive_DMA(&hi2s2, (uint16_t *) first_buffer, 4000 * 4);
HAL_I2S_Receive_DMA(&hi2s3, (uint16_t *) second_buffer, 4000 * 4);

Would there be a delay between the two microphone pairs? Like I2S2 starts first so first element in first_buffer is actually sampled before first element in second_buffer?

If so, is there any way to synchronise between the two I2S?

Thanks

[waclawek.jan · Accepted solution]

> My MCU STM32F407 has 5 I2S peripherals

As far as I know, it has only two SPI/I2S peripherals, and to them attached two I2SExt peripherals.

Are you sure you selected 'F407?

I don't use Cube/CubeMX.

Depending on exactly what type of MEMS microphone you are using, you should be able to handle one pair (i.e. two microphones, usually marked as L/R as in stereo) using one I2S or SPI. You of course then have to perform the PDM-to-PCM demodulation in software.

Some newer STM32 models such as the 'L476 have DFSDM module which is dedicated to this task and can handle multiple inputs.

> Would there be a delay between the two microphone pairs?

Yes.

> If so, is there any way to synchronise between the two I2S?

Yes - simply use only one of them as master, all others as slave, and connect the relevant clock lines externally.

JW

[Phung Tuan Hoang]

I see. Just to be sure when you say relevant clock lines its both CK and WS right? Thanks 😁

[waclawek.jan]

Yes.

If you really use the 'F407, observe the relevant I2S errata, too (slave has to wait until inactive level of WS).

JW