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Nucleo H7S3L8: No GPIO output on ports O and P

fluxyfux
Associate

Hello everyone

I am using a Nucleo H7S3L8 evaluation module am I am trying to get some GPIOs and peripherals to work. I have generated a demo project that toggles a few LEDs and that works. Then I started replacing the GPIO ports (A, B, etc.) and pin numbers in order to get other GPIOs to toggle (I left the rest of the code as-is, really just replaced the letters and numbers). However, I didn't manage to get an output on any of the GPIOs belonging to ports O and P. I tried GPIOO 0 and 4 as well as GPIOP 0-3 and attached the analyzer at CN10 13, 15, 19, 21, 23, 25 with GND at CN10 17 (always one at a time). All these signals do not toggle. Other GPIO banks such as GPIOB and GPIOM work.

Are the O and P ports different than the others? Do I miss some special settings? I will later be using the XSPI there, so I will need exactly these pins.

I appreciate any help!

PS Here are my jumper settings:
JP1: not connected
JP2: connected
JP3: only STLK connected
JP5: connected to 3.3 V
JP6: not connected

1 ACCEPTED SOLUTION

Accepted Solutions
waclawek.jan
Super User

I don't use the 'H7R/S, but my guess is, that those two ports are powered from the VDDXSPI1/2 pins; and that these may also need to be enabled, probably in PWR.

The description of these power domains in DS and RM is, to put it mildly, poor.

Maybe relevant thread?

JW

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3 REPLIES 3
waclawek.jan
Super User

I don't use the 'H7R/S, but my guess is, that those two ports are powered from the VDDXSPI1/2 pins; and that these may also need to be enabled, probably in PWR.

The description of these power domains in DS and RM is, to put it mildly, poor.

Maybe relevant thread?

JW

fluxyfux
Associate

Thanks a lot!
The magic lies in a call to HAL_PWREx_EnableXSPIM1();

waclawek.jan
Super User

Okay, so that just sets a single bit (it took me some time to realize that the 'H7RS Cube is separate from 'H7 Cube, thanks ST!):

void HAL_PWREx_EnableXSPIM1(void)
{
  SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1);
}

 Did this enable both GPIOP and GPIOO pins?

Did you try GPION? From the chips' layouts I'd expect they are bound to VDDXSPIM2 (and thus to be enabled by PWR_CSR2.EN_XSPIM2). Can you please try that, too?

JW