Facing issue to create external loader in IAR Workbench

[Harsh_Gajjalwar]

Debug Logs:

Tue Nov 19, 2024 10:46:36: IAR Embedded Workbench 9.50.2 (C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armPROC.dll)
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx.dmac
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7x5_M7.dmac
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7x5_DBG.dmac
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx_OB.dmac
Tue Nov 19, 2024 10:46:36: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx_TRACE.dmac
Tue Nov 19, 2024 10:46:37: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H7x5.mac
Tue Nov 19, 2024 10:46:37: Time-limited license - IAR Embedded Workbench for Arm, Cortex-M edition 9.60
Tue Nov 19, 2024 10:46:37: JLINK command: ProjectFile = D:\gitESI\TouchScreenGUI-ESI\EWARM\settings\es10_demo_03_es10_demo_03_CM7.jlink, return = 0
Tue Nov 19, 2024 10:46:37: Device "STM32H745XI_M7" selected.
Tue Nov 19, 2024 10:46:37: DLL version: V7.92l, compiled Oct 25 2023 15:21:06
Tue Nov 19, 2024 10:46:37: Firmware: J-Link V12 compiled Jan 24 2024 12:06:13
Tue Nov 19, 2024 10:46:37: Serial number: 602007946
Tue Nov 19, 2024 10:46:37: JTAG speed is initially set to: 1000 kHz
Tue Nov 19, 2024 10:46:37: ConfigTargetSettings() start
Tue Nov 19, 2024 10:46:37: ConfigTargetSettings() end - Took 17us
Tue Nov 19, 2024 10:46:37: InitTarget() start
Tue Nov 19, 2024 10:46:37: JTAG selected. Identifying JTAG Chain...
Tue Nov 19, 2024 10:46:37: TotalIRLen = 9, IRPrint = 0x0011
Tue Nov 19, 2024 10:46:37: JTAG chain detection found 2 devices:
Tue Nov 19, 2024 10:46:37: #0 Id: 0x6BA00477, IRLen: 04, CoreSight JTAG-DP
Tue Nov 19, 2024 10:46:37: #1 Id: 0x06450041, IRLen: 05, Unknown device
Tue Nov 19, 2024 10:46:37: JTAG Chain Identified. Connecting to DAP TAP...
Tue Nov 19, 2024 10:46:37: Successfully connected to selected DAP TAP.
Tue Nov 19, 2024 10:46:37: DAP initialized successfully.
Tue Nov 19, 2024 10:46:37: Enabling debug in 'Standby', 'Stop' & Sleep mode.
Tue Nov 19, 2024 10:46:37: InitTarget() end - Took 14.4ms
Tue Nov 19, 2024 10:46:37: TotalIRLen = 9, IRPrint = 0x0011
Tue Nov 19, 2024 10:46:37: JTAG chain detection found 2 devices:
Tue Nov 19, 2024 10:46:37: #0 Id: 0x6BA00477, IRLen: 04, CoreSight JTAG-DP
Tue Nov 19, 2024 10:46:37: #1 Id: 0x06450041, IRLen: 05, Unknown device
Tue Nov 19, 2024 10:46:37: DPv0 detected
Tue Nov 19, 2024 10:46:37: AP map detection skipped. Manually configured AP map found.
Tue Nov 19, 2024 10:46:37: AP[0]: AHB-AP (IDR: Not set)
Tue Nov 19, 2024 10:46:37: AP[1]: AHB-AP (IDR: Not set)
Tue Nov 19, 2024 10:46:37: AP[2]: APB-AP (IDR: Not set)
Tue Nov 19, 2024 10:46:37: AP[3]: AHB-AP (IDR: Not set)
Tue Nov 19, 2024 10:46:37: AP[0]: Skipped ROMBASE read. CoreBaseAddr manually set by user
Tue Nov 19, 2024 10:46:37: AP[0]: Core found
Tue Nov 19, 2024 10:46:37: CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Tue Nov 19, 2024 10:46:37: Cache: L1 I/D-cache present
Tue Nov 19, 2024 10:46:37: Found Cortex-M7 r1p1, Little endian.
Tue Nov 19, 2024 10:46:37: FPUnit: 8 code (BP) slots and 0 literal slots
Tue Nov 19, 2024 10:46:37: ROM table scan skipped. CoreBaseAddr manually set by user: 0xE00FE000
Tue Nov 19, 2024 10:46:37: I-Cache L1: 16 KB, 256 Sets, 32 Bytes/Line, 2-Way
Tue Nov 19, 2024 10:46:37: D-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way
Tue Nov 19, 2024 10:46:37: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Tue Nov 19, 2024 10:46:37: Reset: Reset device via AIRCR.SYSRESETREQ.
Tue Nov 19, 2024 10:46:37: Hardware reset with strategy 0 was performed
Tue Nov 19, 2024 10:46:37: Initial reset was performed
Tue Nov 19, 2024 10:46:37: Found 2 JTAG devices, Total IRLen = 9:
Tue Nov 19, 2024 10:46:37: #0 Id: 0x6BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Tue Nov 19, 2024 10:46:37: #1 Id: 0x06450041, IRLen: 5, Unknown device
Tue Nov 19, 2024 10:46:38: FL/MAC: Cortex-M4 was stopped to ensure safe flashloader operation.
Tue Nov 19, 2024 10:46:38: Loaded debugee: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H7xx_RAM256K.out
Tue Nov 19, 2024 10:46:38: Target reset
Tue Nov 19, 2024 10:46:43: FL/MAC: Cortex-M4 was started.
Tue Nov 19, 2024 10:46:43: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H7x5.mac
Tue Nov 19, 2024 10:46:43: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H745I-DISCO_QSPI.mac
Tue Nov 19, 2024 10:46:43: FL/MAC: Cortex-M4 was stopped to ensure safe flashloader operation.
Tue Nov 19, 2024 10:46:43: FL/MAC: Configuring QUADSPI GPIO pins.
Tue Nov 19, 2024 10:46:43: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H745I-DISCO_QSPI.mac(88,7): Error: Unknown or ambiguous symbol. use_qspi_bk2_ncs
Tue Nov 19, 2024 10:46:43: Error while calling macro execUserFlashInit
Tue Nov 19, 2024 10:46:43: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H745I-DISCO_QSPI.mac
Tue Nov 19, 2024 10:46:43: Failed to load flash loader: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32H745I-DISCO_QSPI_test.flash
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx.dmac
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7x5_M7.dmac
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7x5_DBG.dmac
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx_OB.dmac
Tue Nov 19, 2024 10:46:45: Unloaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32H7xx_TRACE.dmac
Tue Nov 19, 2024 10:46:50: Loading the J-Link Driver driver
Tue Nov 19, 2024 10:46:50: IAR Embedded Workbench 9.50.2 (C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armPROC.dll)