I am trying to design my own board using the STM32H723ZGT and using the nucleo schematic as a guide. I believed 100nf was typical for the VDD pin bypass capacitors however there is one pin(pin 62) with a 4.7uf capacitor instead. I understand the VBAT and VDDA pins having a different values but why is the C60 bypass capacitor this much bigger bigger? thankyou
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Hello @gigtrent and welcome to the ST Community
As mentioned on the part 7.4 of the AN5419:
"All the power supply and ground pins must be properly connected to the power supplies. These connections,
including pads, tracks and vias should have lowest possible impedance. This is typically achieved with thick track
widths and, preferably, the use of dedicated power supply planes in multilayer PCBs.
In addition, each power supply pair should be decoupled with filtering ceramic capacitors (100 nF) and one single
ceramic capacitor (min. 4.7 μF) connected in parallel. These capacitors need to be placed as close as possible to,
or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but the exact
values depend on the application needs."
Best Regards.
STTwo-32
Hello @gigtrent and welcome to the ST Community
As mentioned on the part 7.4 of the AN5419:
"All the power supply and ground pins must be properly connected to the power supplies. These connections,
including pads, tracks and vias should have lowest possible impedance. This is typically achieved with thick track
widths and, preferably, the use of dedicated power supply planes in multilayer PCBs.
In addition, each power supply pair should be decoupled with filtering ceramic capacitors (100 nF) and one single
ceramic capacitor (min. 4.7 μF) connected in parallel. These capacitors need to be placed as close as possible to,
or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but the exact
values depend on the application needs."
Best Regards.
STTwo-32
