ST25R3911B SPI issues

[qwdwdwwq]

Hello,

I got back to my issues from this post.

I was able to connect wires to SPI lines, and get the measurements to logic analyzer. These are the results:

Logic2 screenshot

Now i can see that the issue is the CS line, but i dont know why it is being changed to HIGH in these short pulses. 

The GPIO config:

/*Configure GPIO pin : SPI1_CS_Pin */
GPIO_InitStruct.Pin = SPI1_CS_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(SPI1_CS_GPIO_Port, &GPIO_InitStruct);

SPI Config:

hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi1.Init.CRCPolynomial = 10;

And the PCB Traces:

---

Edited to apply source code formatting - please see How to insert source code for future reference.

[Andrew Neil]

---

@qwdwdwwq wrote:

Now i can see that the issue is the CS line, i dont know why it is being changed to HIGH in these short pulses. 

Not just CS - it's also on MOSI

Looks like noise being picked up; try looking at it with your scope - in the analogue domain.

What's with the wiggly bits on the SPI traces?

One wouldn't usually worry about equal trace lengths on SPI, but it does look like a good way to pick up interference...

[Brian TIDAL]

Hi,

This issue may be caused by crosstalk in the logic analyzer probe cables.

To reduce crosstalk between wires, twist each signal wire with a ground wire, or at least twist the critical signal wires, such as CS and CLK, with a ground wire.

Ensure that the digital input/output voltage is set correctly, as this setting also adjusts the input logic threshold, which is approximately half of the VIO value.

If the issue still occurs, follow the suggestion from Andrew and use a scope.

Rgds

BT

P.-S. feel free to attach the Salae file in your answer.

[Ulysses HERNIOSUS]

Hi,

besides twisting and putting wires 90 degrees away from the antenna:

• Incorrect SPI config in Saleae. Correct one here:
   
• Enable Glitch filter in Saleae: 
  
• Looking at raw (ignoring the noise): MOSI shows correct 7F (read IC ID) but no activity on MISO
  -> Maybe MISO pin not correctly configured from MCU side? You could open MISO line on MCU side and observe.

Best Regards, Ulysses

[qwdwdwwq]

Thank you for help. I enabled the Glitch filter and the peaks are gone:

 I also checked the CS line with the scope:

[qwdwdwwq]

Also, when i short MOSI and MISO, the MCU is able to read the loopback communication

[Ulysses HERNIOSUS]

Please perform analog signal integrity on MISO line: Record at least two lines, best SCLK and MISO together to see the level on MISO when it should be driving a value.

[Andrew Neil]

Your scope has a USB socket for screen captures:

Please use it - it will give much better results than photographs!

(I'm sure you can also do it via the LAN connection)

[Andrew Neil]

---

@qwdwdwwq wrote:

Thank you for help. I enabled the Glitch filter and the peaks are gone:

---

Of course - the whole point of a glitch filter is to filter-out glitches!

But that only filters them out from the LA display - it doesn't do anything to clean-up the actual signals on the board.

[qwdwdwwq]

Yellow MOSI

Blue MISO

Purple SCK