What is the P_CURRENT in STDES-EVT001V1 design, please help me out to know what exactly it is ?

CRedd.2 · ‎2021-11-18

Peter BENSCH · ‎2021-11-19

Very well spotted!

However, this is the 2nd capacitor bank (C21-22, C25..28, C30-31) with a total capacity of 1320µF directly buffering spike currents. They are therefore directly connected between the drain of the high-side FET and the source of the low-side FET.

The main capacitor bank (C17-20, C23-C24) between VBUS and GND provides a total capacity of 2820µF.

The single-shunt is located between the negative pole of the main capacitor bank and the negative pole of the 2nd capacitor bank you mentioned, which can also be seen in the layout using a GERBER viewer.

Regards

/Peter

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Peter BENSCH · ‎2021-11-19

Welcome, @CRedd.2, to the community!

this topic does not belong to eDesignSuite, so I moved it to Motor Control Hardware.

Regarding your question: P_CURRENT is the phase current, a net that connects to all three phases in STDES-EVT001V1 and is routed via R22, R23, R105 and R106 to ground (single-shunt control).

If the problem is resolved, please mark this topic as answered by selecting Select as best. This will help other users find that answer faster.

/Peter

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CRedd.2 · ‎2021-11-19

Hello,

still i am not clear with this answer, why because as per schematics my assumption is P_Current is ground is this correct or not...VBUS(+) is supply and P_Current is Ground(-)?

Peter BENSCH · ‎2021-11-19

No, all tracks with P_CURRENT are connected.

Then P_CURRENT is connected to the single-shunt resistors mentioned before, consisting of four resistors in parallel.

Finally these shunt resistors are then connected to GND.

So all three phase currents flow through the single-shunt resistor to GND and can be measured jointly by the comparator in U2.

Regards

/Peter

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CRedd.2 · ‎2021-11-19

Dear sir,

Then the below mentioned image design capacitor will not have any negative ..here they connected only VBUS and other side negative should have to connect ...why they connected like these....

Peter BENSCH · ‎2021-11-19

Very well spotted!

However, this is the 2nd capacitor bank (C21-22, C25..28, C30-31) with a total capacity of 1320µF directly buffering spike currents. They are therefore directly connected between the drain of the high-side FET and the source of the low-side FET.

The main capacitor bank (C17-20, C23-C24) between VBUS and GND provides a total capacity of 2820µF.

The single-shunt is located between the negative pole of the main capacitor bank and the negative pole of the 2nd capacitor bank you mentioned, which can also be seen in the layout using a GERBER viewer.

Regards

/Peter

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

CRedd.2 · ‎2021-11-19

Brave sir, i'm clear now.

If any i will be back with questions.

Thank You so much sir!!!!

Kindly, please support as usual.