In the datasheet it is mentioned as "The 8-bit command data are transmitted into L9826 shift registers every CLK falling edge". So which means the master uC sends out the data for every falling edge of the clock and the Slave L9826 samples this data at the every rising edge of the clock. So for this to happen we have set CPOL = 0 & CPHA = 0. Correct me if my understanding was wrong.
Also from the timing diagram we can see that , L9826 shift outs data through SDO pin for every rising edge of the clock. So in that case the master uC should sample this data at falling edge of the clock.
So there is conflict between the sampling point uC and L9826 for their respective input data.
What should be correct setting for CPOL and CPHA?
At what edge of the clock the datas are sampled in both Master and Slave?
Thanks
Rajmohan A
