L6474 grounding/layout recommendations

maurizio · ‎2014-06-03

Posted on June 03, 2014 at 11:22

The L6474 chip provides three ground pins (PGND, AGND, DGND) as well as a thermal pad (EPAD) connected internally to all three of the above. If I understand the chip's block diagram correctly (datasheet, p. 7), PGND and AGND are tied together within the chip. In the eval board a single ground plane is used for PGND, AGND, DGND and EPAD. In our application it is necessary to avoid coupling of noisy analog currents to the digital domain as well as to the I/O area of the board. Splitting DGND and AGND and using optocouplers may make sense but we need to prevent ground loops. e.g. due to chip-internal connections. Are there any recommendations from your side on this issue?

#board-layout #grounding #l6474

Enrico Poli · ‎2014-06-25

Posted on June 25, 2014 at 16:34

Dear Maurizio,

All the ground pins are internally connected and disalignment between the ground pins should be avoided, so from the layout point of view you should consider all the ground pins of the IC as ''power ground''.

The indication of the PGND pins can help the layout optimization making it clear that the power stage currents flowing through these pins.

Enrico