Hello Folks
The L6470 datasheet (see snapshots provided by Jacek) clearly says that Vreg should be connected to VDD, as they are not connected internally. Further, VDD should have 10uF Cap to work properly.
Surprisingly, the X-NUCLEO-IHM02A1, which has two of these chip in daisy-chain mode, never connects VDD with Vreg, and there is no 10uF Cap on VDD, and VDD is connected via external power supply. That's fine. However, datasheet says that Vdd and Vreg can be tied all together with external power supply. I have yet to see a schematic by ST where that has been implemented.
On another side, EVAL6470PD schematic also connects Vreg and Vdd of one single L6470PD. That seems to be one of the method prescribed by datasheet. However, it's not mentioned or clarified that can we have both Vdd and Vreg connects to external 3.3V power supply in case of multiple L6470 are used?
My application requires daisy chaining of four L6470PD devices.
Now, my Question is if I have multiple L6470PDs then may I still connect VDD with Vreg? May I have all the Vdds and Vregs of all the L6470 CHIPs tied together and then connect them with external 3.3V supply? Is that fine? or shall I strictly follow the schematic X-NUCLEO-IHM02A1 for multiple L6470?
I have designed a PCB by following design suggestions provided by datsheet. However, it never works properly. The driver behaves erratically as it has mind of its own.
The datasheet is not at all aligned with schematic attached of X-NUCLEO-IHM02A1. I am bamboozled right now. A serious help is required!!
FYI, please see the attached schematic of X-NUCLEO-IHM02A1 and my attached schematic snapshot below for your reference:
Hello JSang.1
Thanks a lot for sharing this with community and maybe I can try to help you. First I had a pleasure to see your schematic and I found two problems which might give you "erratic" behavior of the Chips.
- SPI bus
Both L6470 share the same SPI bus so SDO/SDI/CK lines need to be shared in the same way with both chips CS - chip select should be pin which allow your control unit to pick which one you wanted to activate. So I am seeing that CS line is not individual for each chip , and also the there is so net mismatch for SDO and SDI lines.
- The STBY/RST | Sync_X1 and Flag_X1 lines you pulled up to different voltage that VDD. So since I don't see the full circuit and your final solution if want like tat then the VDD lines need to be tight this VDD_01 and VDD_02 respectively. However if you supply both chips from the same 3.3V bus then VDD_01 and VDD_02 in my opinion should be on the same level.
Now let me explain what I have learned about VDD and VREG. So This L6470 internally contain 3V regulator and it output is present on the VREG pin. If you tight it with the VDD you need to remember about one important mechanism which I was not aware at the beginning. If you generate your 3.3V from different power supply which supply for example your MCU , stepper motor driver etc... , remember that VREG 3V signal in present when you supply the chip with the voltage which you plan to use to supply stepper motor. So in other words if you keep them connected and you disconnect the 3.3V line for you MCU and driver , but the 24V will be still present then because you have VDD and VREG together you will still back feed your MCU with 3V signal. This is not recommended from ST to use VREG line to supply. What I did I am simply disconnected them and add the bypass caps to keep nice stabilization for the internal Vreg (see below ). Now it I disconnect 3.3V line my logic system is turned off even if 24V line is present on the Stepper driver.
So if you don't mind I was adding some modification on your schematic to present suggestions ( schematic is worth 1000 words )
ps. Please add some more capacitors for all VSA and VSB pairs...
I hope my explanation make sense and ask more if you needed I will be more than happy to help.
With Best Regards.
Jacek Pieczaba
