Posted on August 14, 2013 at 18:46Thanks Enrico, POL = 1 and PHA = 1 did NOT work (could not even get the status register), but we solved the problem by changing from (POL = 0, PHA = 1 to POL =1, PHA = 0). According to the TI and ST documentation, this should NOT work. On TI document slau049f.pdf page 294 the definition of the bits:
CKPH Bit 7 Clock phase select. Controls the phase of UCLK.
0 Normal UCLK clocking scheme
1 UCLK is delayed by one half cycle
CKPL Bit 6 Clock polarity select
0 The inactive level is low; data is output with the rising edge of UCLK;
input data is latched with the falling edge of UCLK.
1 The inactive level is high; data is output with the falling edge of
UCLK; input data is latched with the rising edge of UCLK.
On ST L6470 datasheet page 38:
The SDI is sampled on the rising edges of the CK. ... The SDO is latched on the falling edges of the CK.
As as you can see, it should NOT work, but it does anyway.
