2004-03-15 01:51 AM
2004-03-11 12:34 AM
I'm working with the ST72264G u-C.
I'm using Timer A in ''one pulse mode'', and I want to use Timer B as ''output compare'' to indicate when a period of time has elapsed without output pin. (just to get interrupt when a period has elapsed). In my application I want Timer B to be stopped until I enable it wait for the output compare interrupt and disable it back. Since Timer B is free running, when I enable the interrupts using ''rim'' I get a timer B interrupt although I already set the TIMD bit in the CSR (and preformed a read from the CSR/OCBLR to clear the OCF bit). Can anyone advise how the get rid from the first unwanted interrupt?2004-03-14 11:56 PM
It is not the normal behaviour. Could you attach your code ?
2004-03-15 01:51 AM
I suspected that I worked with a faulty chip.
I replaced it and everything is working. Thanks