STR912 Boot Bank1 @ 96MHz

[dschuler9]

Posted on June 08, 2009 at 19:00

STR912 Boot Bank1 @ 96MHz

[dschuler9]

Posted on May 17, 2011 at 09:58

as so many others here, i have massive problems with booting the str912 from bank1 and switching to bank0.

I have managed to boot from bank1 and jump between both banks without any problems when running the controller at 48MHz. Since so many people seem to have problems doing this, i have attached a sample uVision project (see notes below). However as soon as i set the clock to 96MHz, this wont work anymore. Sometimes there also seems to be different behaviour depending on the type of reset (System / Global) but i cannot exactly confirm this. Did anybody ever manage to run the STR912 at 96MHz when booting from Bank1??? (The code works fine when booting from Bank0). Can anybody confirm this behaviour?? [EDIT] The real problem is not the CPU running at 96MHz but the FMI clock. It also works when fMSTR & RCLK is 96MHz and the FMI Clock Divider is set to RCLK/2... [/EDIT] My code is based on the ''Configuring the STR91xFA MCU for optimum CPU performance'' example from ST. In this PDF, ST states:

Quote:

When booting from bank1: � Use OSC as the default clock source. � If you want to run the CPU @ 66 MHz or higher, the PLL configuration can be done in the application code (“C� code) instead of in the start-up assembly file. � The Flash wait state selection instructions must be executed from SRAM as it is not possible to read while writing in the same bank. Why do we have to use OSC as default clock source (i tried this without success) ? Why should the PLL configuration be done in the C-Code? Whats the difference? I wrote a small assembly file to load the flash wait state selection instructions to RAM (since i setup the wait states from the startup assembly file, i cannot use the built-in RAM function support....) Whats the matter with executing code in Bank1 at 96MHz?? Any suggestions / discusion is highly appreciated. I'm almost going crazy with this, already lost about one week trying to get this stuff working... Some notes on the project i attached: This is a Keil uVision project and running on a Keil MCB-STR9 evaluation board with STR912FAW44 silicon rev. H. It assumes that 8 LEDs are connected to Port7 and two push buttons connected to P3.5 and P3.6. Both inputs must be pulled high via resistor and pulled low by the push buttons. The button on P3.5 is used to remap the flash banks (both directions; Bank0 -> Bank1 and Bank1 -> Bank0). The button on P3.6 resets execution of the currently selected flash bank to address 0. The bank switch is done from a SWI handler to set the CPU into supervsior mode and avoid problems with execution of the startup code. [ This message was edited by: d.schuler on 23-03-2009 11:39 ]

[bkurz]

Posted on May 17, 2011 at 09:58

If I remember correctly, there was a note in the errata or one of the documents that said for the larger memory devices (1M/2M), that the FMI_CLK must be set to 48MHz max. I do not recall what the reasoning behind this was, but I do recall having to set my FMI_CLK to 48MHz, even though at 96MHz my system still seemed to work fine. I was booting an STR912FAW47X from bank 1, uploading code via HTTP, then transitioning to bank 0. The biggest problem I had was with getting the interrupts trampoline in ram implemented to allow me to use interrupts in both my bootloader and main application.

/Brian