2005-03-22 04:41 PM
Problem with Falling edge Interrupt(Flite09) with switch
2005-03-20 05:32 PM
Hello,
I am working on an application using ST7FLITE09.I have connected a push button switch to one of ext. interrupt pin(PA7).I have connected a pull-up register to that pin.Other end of this switch is in GND. Normally this pin is in ''high'' state.Whenever i pressed the switch it will come to GND, so will be in low state for the time the switch is in pressed cond.if i release the switch it will again go to high state.So i am using this switch press event as ext Interrupt(falling edge cnfig.).My aim is whenever i press the switch one of my register should increase by 1(++SwitchpressCount). It's working fine in normal cond. But problem arises when I momentarily switch the +5V power to my application ON and OFFand do it several times in quick sucession.I have seen my counter is incresed even though i haven't pressed the switch. What could be the problem?why micro is sensing the Int.Yes during Power ON/OFF , i/p state will come from high to low.it may sense. How could i rectify the probs?ie counter should not increment during that supply power interruption time? Normally when power goes the i/p pin(PA7) will come to 'low' state. I have configred as falling edge thro EICR register.Now Interrupt will cnsider when the pin come from 'high'(5V) to 'low'.My question is how much (mininimum value)should be the low value for micro to consider as interrupt(falling edge)?. Any help will be appreciated. Thanks, Arup2005-03-21 03:13 AM
Arup,
if you want to disable the SwitchpressCount during power ON or OFF, you can reset bit 7 of PAOR which is related to PA7. When this bit is set, an interrupt will be generated whenever PA7 is low, i.e. the button is pressed. In this manner, you can increase SwithpressCount only when it is safe to do. Regards, EtaPhi2005-03-21 07:34 PM
hello,
Thanks for your suggestion.yes interrupt will disable if OR bit is reset.But The ''momentarily power ON/OFF condition'' is a real time condition.so If i can detect that condition then i will be able to ignore the interrupt by reseting the OR bit during that time frame.Now question is how to detect that condition??? best regards, Arup2005-03-21 07:52 PM
Arup,
the power DOWN condition can be detected by the LVD machinery. You have to handle a new interrupt which is fired whenever the power supply drops below a certain limit. The power ON condition is dectected by the reset circuitry which holds the micro in the reset state until the power supply rises above a fixed limits. All these limits are controlled by some option bytes. Please, see your documentation for more details. Regards, EtaPhi2005-03-22 04:41 PM
This is a strange pb. In my opinion the momentarily Power-on/off shall cause the Reset unless it is out of LVD range. If the reset is recognised properly this shall reset the PAOR register and hence the interrupt capability on the pin shall be removed at reset unless configured by the software.
Try putting 100nF capa on interrupt pin.