Posted on November 02, 2007 at 10:33The 'resync' procedure is to clear a so called 'stuck bus' condition. This can occur for example if you start reading from the eeprom/slave and don't ( for what ever reason, maybe a soft reset ) finish the sequence properly. The bus can be stuck in a condition were the slave (e.g. eeprom) could be driving the SDA line low i.e. logic zero when you stopped clocking the part. Under this condition the master cannot regain control as the SDA is held low by the slave.
The condition is cleared by clocking the part upto 9 times whilst monitoring the SDA line and waiting for it to go high again.
The following is an example of a bit banged I2C Init routine which checks and clears this condition before programming the port pins as SCL and SDA.
BYTE I2C_Init(void)
{
BYTE i=9; // may need to clock a slave upto 9 times if it is holding the bus low
// Initially program SDA as input and SCL as output high
I2CPORT_OR&= (BYTE)~SCL_PIN;
I2CPORT_DR |= (BYTE)SCL_PIN; // Make sure of open drain output
I2CPORT_DDR|= (BYTE)SCL_PIN;
I2CPORT_DDR&= (BYTE)~SDA_PIN; // make sure of floating input
I2CPORT_OR&= (BYTE)~SDA_PIN;
// Now check for a stuck bus
while( ((I2CPORT_DR & SDA_PIN) == 0)&& i ) // Is SDA held low by slave ?
{
// clock next bit from slave driving the bus
SCL_LO;
SCL_HI;
i--;
}
if(i == 0)
{
return 0; // still stuck we're screwed need to fail and power off
}
else
{
// got good bus here
I2CPORT_DR|= SDA_PIN;
I2CPORT_DDR|= SDA_PIN ; // now set SDA output high
// now have idle condition
return 1;
}
}
