Posted on January 24, 2006 at 13:06 Hello Looking,
If the master wants to share its internal XBUS peripherals (XRAM in your case), it has to set the XPERSHARE bit in register SYSCON (before EINIT instruction).
Master Slave
HOLD <--> BREQ
HLDA <--> HLDA
BREQ <--> HOLD
Master (DP6.7 = 0, in PSW register HLDEN = 1)
Slave (DP6.7 = 1, in PSW register HLDEN = 1)
The on-chip XRAM is accessed without any wait-states, using 16-bit de-multiplexed bus cycles.
In order to be able to access the 2 XRAM modules, they must be enabled by setting XPEN bit in SYSCON register and XRAM1EN & XRAM2EN bits in XPERCON register.
For more details, please refer to the ST10F276 user's manual (section 3.4 The On-Chip XRAM).
Find enclosed an application note which could help you.
Regarding your second question, if i had well understood, it is not possible to allocate 1 Mbyte for the XRAM2. The maximum XRAM2 size is 64Kbytes that you can only reduce using XADRS3 register.
For more details, please refer to the ST10F276 user's manual (section 9.7 The XBUS Interface) where examples of memory mapping are given.
I hope this helps you,
With kind regards,
Najoua.
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Attachments : ap1601910_C167CR_Master_Slave_Bus_Arbitration.pdf :
https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I0KD&d=%2Fa%2F0X0000000bXN%2F5UAO1jlCuKAounSPZXuBXPwvdS7f0oqFPOKc8H6d8A4&asPdf=false
