Posted on May 17, 2011 at 11:50I'm developing a usb application firmware for uPSD3433EV chip.
I met with the following problem.
After the firmware changed FIFO ownership into SIE from
CPU (BSY=0 -> BSY=1), chip sends ACK to host by arrival of data packet.
However, at this time FIFO ownership does NOT turn into CPU. And interrupt is not generated, too.
As a result, firmware loses an opportunity to get this data because
of next data overwrites this data.
When chip receives data packet 64 times in succession in one time
of control OUT transaction,
this phenomenon occurs with about 2 times frequency at random.
About 62 data packets arrive normally. As interrupt is generated respectively, firmware can get these data.
There are some case that the chip succeeds in receiving all data.
This phenomenon occurs with other same chip.
Is there the person who met with a similar problem and solved this ?
