2007-08-12 07:35 PM
2011-05-17 02:31 AM
Hi everyone,
I'm confused about Timing rules that is described in page 40 of UM0388. The No.4 rule is described as below, ''The number of Write Enable wait states must be greater than the Address Latch Address Enable time in mux mode (WSTOEN > ALE).'' In the previous section said, WSTOEN: Read EnableIs there some mistake in UM0388?