STR73x CAN clock source

[HNguy.1]

Hello,

we are using STR73x for our application.

We developed our own CAN boot loader that can download our application code ​to the flash and reboot the system.  The reboot works fine.

But we decided to change the application codes such that it does not reinitialize oscillator clock selection (CMU block) and does not turn off PLL and relock it again, the CAN fails to work but the UART debug still works correctly at the right baud rate. 

we are confused on what may happen.  That is why we want to ask if CAN is configured with MCLK which is driven by PLL clock or by OSC clock. 

Can you please let us know what else can impact CAN clock source like that?

Thanks,

Henry

[Tesla DeLorean]

Pretty much you're going to have to review the reference manual, and likely decode the clock and registers settings. Typically my approach is to write software to output and compute clock settings, and I'd then probably drive a pattern on the CAN bus in loop-back mode, and scope the signals to confirm the clocking parameters have been decoded properly.

Seems a very antiquated part to be using in 2018, you might be able to find contractors with skills, or ST many be able to provide you with a list. If the project is historical you might check availability of former colleagues who worked on it.

https://www.st.com/content/ccc/resource/technical/document/reference_manual/16/04/e0/5e/49/df/42/a5/CD00164537.pdf/files/CD00164537.pdf/jcr:content/translations/en.CD00164537.pdf