Posted on November 02, 2006 at 12:48Hello,
I just started using the IAR KickStart Kit w/STR712 evaluation board. I downloaded the up-to-date library below:
STR71x Standard Software Library 3.1 Jan-2006
There appears to be a problem in the code or an error in the STR71x Microcontroller Reference Manual Rev 7. (Nov 2005)
The reference manual states on page 237/349:
Bit 9 = CPHA: Clock Phase Select.
Used with the CPOL bit to define the master-slave clock relationship. When CPHA=0, as soon as the SS goes low the first data sample is captured on the first edge of SCLK. When CPHA=1, the data is captured on the second edge.
Bit 8 = CPOL: Clock Polarity Select.
When this bit is cleared and data is not being transferred, a stable low value is present on the SCLK pin. If the bit is set the SCLK pin will idle high. This bit is used with the CPHA bit to define the master-slave clock relationship.
0: Active high clocks selected; SCLK idles low.
1: Active low clocks selected; SCLK idles high.
On the other hand the STR71x Library software reads:
/*---------------------------------------------------------*/
inline void BSPI_ClkFEdge(BSPI_TypeDef *BSPIx, FunctionalState NewState)
{
if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_CPHA_Mask;
else BSPIx->CSR1&=~BSPI_CPHA_Mask;
}
inline void BSPI_ClkActiveHigh(BSPI_TypeDef *BSPIx, FunctionalState NewState)
{
if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_CPOL_Mask;
else BSPIx->CSR1 &= ~BSPI_CPOL_Mask;
}
/*---------------------------------------------------------*/
If these two parameters are enabled, the bits are set by Oring in the Mask. Although the reference manual reads they should be cleared. I've also found another bug in the Timer software.
Is there a running bug list for the STR71x library software? If so, could you please post it to help speed up my development. Thanks.
EDude
