ST7FLITE2 documentation errors

fggnrc · ‎2004-10-18

Posted on October 18, 2004 at 12:52

fggnrc · ‎2004-10-12

Posted on October 12, 2004 at 09:51

My apologies if this is not the right place to post this information...

I found some errors in the rev 3.0 documentation of the ST7FLITE2 that was posted this month.

The first one is in the figure 13 at page 25.

The line going from fOSC to bit 7 of MCCSR is clearly wrong: it has to go the mux controlled by SMS (bit 0 of MCCSR)

The second one, is in figure 6 at page 15.

I do not understand why the internal EEPROM bus width is 128 bits wide.

If a row contains 32 x 8 bits (= 256), how are they transmitted to the memory matrix?

As regards EEPROM write cycle, the documentation says that up to 32 bytes can be programmed in the same cycle, but does not say what I have to do to change only a byte.

In application note 1324, I saw this code snippet:

LD RCCR,A

BSET EECSR,#1

LD $1003,A

BSET EECSR,#0

wait

BTJT EECSR,#0,wait

Does it changes only the byte stored ad $1003 and leaves the others in the range $1000 - $101F unchanged?

Thanks in advance,

EtaPhi

wolfgang2399 · ‎2004-10-13

Posted on October 13, 2004 at 11:30

Hi EthaPhi,

I think this is really the best place to post information about errors.

As you did, I found some errors still in the new Rev. 3.0.

Chapter 11.2.3 AUTORELOAD TIMER:

-1: The figure 35 is fully confused and you only can understand what they meant if you understand the whole function in respective to inverter, TRAN, counter overflow and OPx. Annoying!!!!

-2: The figure 36 is in contradiction to figure 37:

(With OE=1,OPx=0) the PWM signal goes high on counter = ATR (fig 36) and on counter = ATR+1 (fig 37). Figure 37 seems to be the right one.

Respecting to your question how to write one single byte to EEPROM I found the following text in the datasheet on page 16:

When PGM bit is set by the software, all the previous

bytes written in the data latches (up to 32) are

programmed in the EEPROM cells.

That's correct and really means: only these bytes are written to EEPROM and it can be one single byte.

Regards

WoRo

jatin · ‎2004-10-18

Posted on October 18, 2004 at 10:21

EtaPhi,

Thanks for your feedback.

1. Regarding the Figure 13, page25, you are right. The datasheet modification will be done as per your feedback.

2. Regarding the EEPROM figure6, page 15. It is correct. The bus is internal to the controller and is not accesible to the user.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells.The EEPROM programming time is same for 1-32 bytes. See page 102/131.

Woro,

Regarding the figure 36/37. The figure 37 is the precise version of figure 36. Both figures are correct.

wolfgang2399 · ‎2004-10-18

Posted on October 18, 2004 at 12:52

Hi Jatin,

sorry but I must insist:

As I read it

Figure 36:

The PWM-signal goes high at the beginning of the state COUNTER = ATR

Figure 37:

The PWM-signal goes high at the end of the state COUNTER = ATR

Where is my mistake??

Regards

WoRo

wolfgang2399 · ‎2004-10-18

Posted on October 18, 2004 at 12:52

Hi Jatin,

sorry but I must insist:

As I read it

Figure 36:

The PWM-signal goes high at the beginning of the state COUNTER = ATR

Figure 37:

The PWM-signal goes high at the end of the state COUNTER = ATR

Where is my mistake??

Regards

WoRo