ST72324 PWM

[dhaak]

Posted on March 02, 2004 at 02:27

ST72324 PWM

[dhaak]

Posted on February 27, 2004 at 18:08

I am attempting to use ST72324 PWm for lower freqyuency signals (175 - 335 Hz) with set duty cycle. Whenever I write new hi and lo bytes (in that order), I get pulse gitches:

LD A, freq_hi LD TBOC2HR, A ; load hi byte into register for PWM LD A, freq_lo LD TBOC2LR, A ; load lo byte into register for PWM set up with: LD A, $04 ; Load 00000100, 1) OLVL2 bit = 1, which will force a high LD TBCR1, A ; on the OCMP1_A pin after every successful comparision between ; the TBOC2HR & TBOC2LR and the 16bit timer, 2) OLVL1 bit = 0, ; which will force a low on the OCMP1_A pin after every ; successful comparision between the TBOC1HR & TBOC1LR and the ; 16bit timer */ LD A, $94 ; Load 10010100, 1) Dedicate OCMP1_B pin to output LD TBCR2, A ;compare function, 2) Activate PWM mode, 3) Divide Fcpu by 2 */ What am I doing wrong???

[sjo]

Posted on March 01, 2004 at 06:12

This is taken from the ST knowledge base:

Question: 0 Is the PWM (Output compare registers) buffered, so that if you change the registers on the fly it will not cause the PWM output pin to ''glitch''? Answer: As long as the PWM frequency (ie OCPM2 register) is not changed, the PWM duty cycle can be changed on the fly without causing the output pin to stay at the same level for one timer overflow period. To make sure the signal does not stay at OLVL2 for one PWM period during the change, the OCMP1 registers are written (higher byte and then lower byte) before the counter reaches the OCMP1 value. Regards sjo

[dhaak]

Posted on March 01, 2004 at 11:14

Thanks, then I must check for the OCMP1 value before writing new frequency. This was poorly written in their datasheet and their apps people did not know that either.

''Any new values written in OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWm output pin (OCMP1)''

[dhaak]

Posted on March 01, 2004 at 11:24

Not being a micro guru.....

Would a purely software method be more feasible to do than using a variable frequency PWM method? My pulse width is not a concern, just the frequency.

[dhaak]

Posted on March 01, 2004 at 13:12

Found that if I check the alternate High Reg (ACHR) for a value (pulse width). If I write before that I should be safe, but never write after that count. Things seem to work so far.

Thanks again Sensor

[jatin]

Posted on March 02, 2004 at 02:27

You can also reset the counter by writing into the counter low register(CLR).