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Question about Writeprotect (WP) for I2C EEPROM, eg M24M01E

Strooom
Associate III

For these EEPROMs there is a WP pin, which must be (active) low to enable write operations. I am driving this pin from an MCU, (ie. it is not tied to GND).

Also these EEPROMs need some time after a write command to effectively write the data into the EEPROM, eg. 3.5 ms max.

Now my question is : does the WP need to stay active low during those 3.5 ms after the write command ?

 

1 ACCEPTED SOLUTION

Accepted Solutions

Ok, you see from timing diagram : /WC has to be lo before write sequence starts and can stay lo or go high after full sequence, including last ACK and I2C STOP .

The eeprom may be busy internal some more time (..4ms) , so you should be sure, not to switch power off in this time.

WC state is no more important here, the internal write is in execution.

And the time, /WC has to be lo after last ACK+STOP , IS in the ds :

AScha3_0-1712410666974.png

 

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3 REPLIES 3
AScha.3
Chief II

This you should see in the datasheet of your eeprom.

If you feel a post has answered your question, please click "Accept as Solution".

Sure, but the datasheet doesn’t answer the question, that’s the reason I ask it here.

Attached is a screenshot of M24M01E-F datasheet. It shows some delay between last I2C databyte and rising WC, but no timing is defined…

I could also try to find out with some experiments, but I prefer a response from someone who knows about the internals of such devices.

Ok, you see from timing diagram : /WC has to be lo before write sequence starts and can stay lo or go high after full sequence, including last ACK and I2C STOP .

The eeprom may be busy internal some more time (..4ms) , so you should be sure, not to switch power off in this time.

WC state is no more important here, the internal write is in execution.

And the time, /WC has to be lo after last ACK+STOP , IS in the ds :

AScha3_0-1712410666974.png

 

If you feel a post has answered your question, please click "Accept as Solution".