problem with STLITE09 watchdog timer

[andrea239955_stm1]

Posted on December 20, 2007 at 11:41

problem with STLITE09 watchdog timer

[andrea239955_stm1]

Posted on December 10, 2007 at 12:46

Hello everybody,

I'm experiencing the following problem: I want to use the watchdog feature with the ST7LITE09 controller, but, if I follow the instruction of the manual it doesn't work. In detail: The manual specify to set the WDGD bit of the LTCSR before the WGDE bit (see manual at page 50, release october 2006). In this way, if the watchdog timer expires after the 2mS the microcontroller doesn't reset and remains hanged. Instead, if I set the WGDE bit before the WDGD everything works. Did anyone else experienced the same thing? Here is the initialization of my code: sim ld A,#%10111111 ; PORT INIT ld PADDR,A ld A,#%10111111 ld PAOR,A ld A,#%00000000 ld PADR,A ;--------------------------------- ld A,#%00000000 ld PBDDR,A ld A,#%00000000 ld PBOR,A ld A,#%00000000 ld PBDR,A ;--------------------------------- ; EXT INTERRUPT SETTING ;--------------------------------- ld A,#%10101010 ld EICR,A ;--------------------------------- ; LITE TIMER INIT ;--------------------------------- ld A,#%00110011 ; enable intr 2ms @8MHz ld LTCSR,A ; enable WD and reload it ;--------------------------------- ; ADC INIT ;--------------------------------- ld A,#%01000000 ; speed=1 ld ADCCSR,A ;--------------------------------- ; CK INIT ;--------------------------------- ld A,#$80 ld RCCR,A ;--------------------------------- ; RAM CLEAR ;--------------------------------- bset LTCSR,#0 ; WD reload ld X,#$80 ; Clear RAM0 area [0080h-00BFh] in_100 ld A,#0 ld (X),A ld A,X cp A,#$BF jreq in_quit inc X jp in_100 in_quit rim ; Enable Interrupt any idea? thanks to everyone !

[fggnrc]

Posted on December 11, 2007 at 04:02

Andrea,

in my opinion the problem lies in the way you initialize LTCSR. The istruction ld A,#%00110011 ; enable intr 2ms @8MHz ld LTCSR,A ; enable WD and reload it activates the watchdog and delays its expiration AT THE SAME TIME. This is somewhat different from what the datasheet says. To initialize the watchdog, I would write this code: ld A,#%00110001 ld LTCSR,A bset LTCSR,#1 ; This clears also the Time Base Interrupt Flag Your initialization sequence contains also some things that I would write differently. The first one is the internal RC oscillator initialization. This should be the first thing to do, otherwise the micro will init the I/O ports, the interrupts and the lite timer at about 50% of the nominal clock speed. The second one is the RC initialization, which I would write as LD A,$FFDE LD RCCR,A since the $80 gives a worse precision than the calibration value. The third is the way you clear the RAM. In my opinion it is better to use the following instructions: LD A,#0 LD X,#$BF clr_RAM: LD (X),A DEC X CP X,#$7F JRNE clr_RAM Regards EtaPhi

[andrea239955_stm1]

Posted on December 18, 2007 at 07:44

Hi EtaPhi,

Thanks for your reply. I'm aware of the secondary suggestion you gave me, but, talking about the watchdog... Yes, I tryied to make the reload/initialization as you say but it doesn't work. I tryied the following: 1) as per my message ld A,#%00110011 ld LTCSR,A 2) same as your suggestion: ld A,#%00110001 ld LTCSR,A bset LTCSR,#1 3) one variation... (doesn't work) ld A,#%00110000 ld LTCSR,A bset LTCSR,#0 bset LTCSR,#1 NONE of these are OK. I mean with one of these initialization, if the watchdog timer elapses no reset occur (n.b. reset pin of microcontroller is not connected: no pullup, no pulldown, nothing). The only way to make it work is the following: ld A,#%00110010 ld LTCSR,A bset LTCSR,#0 For me the problem is solved, but I wonder if there's a way to make it work following the ST datasheet. regards, Andrea Rosati

[sjo]

Posted on December 19, 2007 at 11:30

May or not be relevant, but i had a issue with the watchdog not reseting the device.

We were using internal rc but not the PLL. The watchdog would only reset the device if the PLL was set to x8 (default for the device). The only other thing i do is read the LTCSR reg to make sure the WDGRF is clear. in c but the idea is the same: /* clear watchdog reset flag */ LTCSR; /* enable software watchdog */ SetBit( LTCSR, WDGE ); Cheers Spen

[andrea239955_stm1]

Posted on December 20, 2007 at 11:41

Hi Sjo, glad to read from you again! (we met in some other ST forum... softec if I remember well)

In my application I use the internal RC with the PLL x 8 to obtain an RC at 8mHz. In addition I also use the LVD at the medium value. The complete option byte I use is $FE : $AD. Now I will try your suggestion to clear the WDGRF by reading the LTCSR. Thanks very much and regards, Andrea