Posted on February 26, 2006 at 02:09Does any one have the original HDLC IP doco - was this ST IP or some one elses they have licenced - if so is their doco available.
I pointed out several errors in the STR71x reference manual that were corrected in the November reference manual but now that I come to use it there are more areas that are inconsitent, unclear or incorrect.
ISSUE 1 ______________________________________________
From the November Reference Manual.
- Transmission
As long as the bit TEN in HDLC_PCR is low only idle or flag interframe are transmitted
according to the value of ITF bit of HDLC_TCTLR.
To start a Frame transmission, the following must be written:
– data into the Transmission Buffer (all the packet or until the Buffer is full) see Figure 77,
– the number of bytes to be transmitted in the HDLC_TFBC register
– bit TEN must be set to ‘1’ (by software or by hardware if HTEN = 1).
As soon register HDLC_TFBC is set, the HDLC starts postamble transmission, and reads
data from the buffer until it is half empty or the number of transmitted bytes matches the value
in HDLC_TFBC register.
In the first case an TBE (Transmission Buffer Empty) interrupt will be generated whereas in
the second case the CRC is evaluated, the closing flag and the postamble are generated.
Can you explain why the unit starts transmission with postamble and not preamble.
According to this when HDLC_TFBC is set the transmission starts but this is middle operation in above list. Surely it is TEN that must start TX or you would not be able to start a transmission from the timer.
And according to this, transmission stops when buffer is half emptied but it does not say what actual action restarts the rest of the transmission. It also does not make sense to stop at half empty I suspect it does not stop but continues on and simple generates as interrupt at half empty.
But if TEN starts the transmission why in flow chart of Figure 77 does the write to TEN precede setting of HDLC_TFBC. I assume TXByte Count Reg in this drawing is the HDLC_TFBC register. The description in the legand is ''TXByte Counter = Transmitted byte counter'' which is not very specific.
Is it in fact transmission starts when TEN is true and HDLC_TFBC is not zero but this can happen in either order?
ISSUE 2 _______________________________________________
The half buffer bits RBR and TBR in HDLC_PSR are defined as follows in the Nov reference manual.
Bit 3 = RBR: Receive half Buffer Ready
When 0 , the low half of the receive buffer is full.
When 1, the high half of the receive buffer is full.
Bit 2 = TBR: Transmission half Buffer Ready
When 0, the low half of the transmission buffer is empty.
When 1, the high half of the transmission buffer is empty.
But their state when TX are both empty is not described nor when RX are both empty. The TX matter is of prime importance. It is not clear whether when a new transmission is started whether you start writing into the low haf of the buffer. If you read the TBR bit and start the write there is no certainty that the TBR bit will nto change when you change other HDLC registers.
What are ALL of the conditions that can change these bits and if you send / receive short (128 or less bytes) packets are they always starting at the low buffer.
The doco also does not give enough information to know how or if it is possible to be writing TX buffer whle last packet is still going (by starting in the other half TX buffer).
General ___________________________________
I am not looking for application assistance just a clear concise and accurate description of the peripheral. Does such a document exist ? Does some one have authoritive answers to the above issues.
I am loathed to use the HDLC library supplied as a reference as I have already found bugs in this that clearly show buffer rollover was untested and faulty.
Code:
