EMI timing and data size

abird · ‎2006-06-23

Posted on June 23, 2006 at 16:26

abird · ‎2011-05-17

Posted on May 17, 2011 at 09:30

Hi

1. Are there timing diagrams available for EMI read / write cycles using the various different multiplexed / non-multiplexed modes? I couldn't find them in the reference manual of data sheet.

2. Is a read / write operation always 32-bit or 8/16-bit depending on the data bus size? Ie. Does the EMI controller generate a sequence of read / write and address increments based on the data bus width (similar to the STR7)?

Eg. With EMI configured for 8-bit data bus width, does a read operation read 32 bits by generating 4 reads on the EMI and incrementing the address between each read? How about for a write operation?

3. Related to question 1 and 2. What is the effect and timing when using one of the paging modes?

Possibly I've missed something in the docs or misunderstood - timing diagrams would really help.

Thanks in advance,

Andy

abird · ‎2011-05-17

Posted on May 17, 2011 at 09:30

Hi

OK, I found the timing diagrams in the data sheet.

But I am still not clear whether accessing an EMI memory address from the CPU is a 32-bit operation?

Eg. In say non-multiplexed 8-bit mode, does reading an address from EMI memory to a processor register just read 1 byte of data from the EMI? Or does the EMI controller issue a sequence of 4 read operations at contiguous addresses to read 32 bits of data?

Thanks,

Andy