Posted on August 02, 2003 at 04:58 I manage to use demux bus of F269 to access SDRAM chip directly. I plan to derive SDRAM clock from F269'CLKOUT(divided by 4 or , then connect SDRAM /CS to F269 /CSx, SDRAM data lines to data bus and others to address bus.
The feasibility of my scheme is determined that the start point of external bus cyle should always coincide with the rising edge of SDRAM clock(or have a fixed delay). So I want to know if there exists a fosc/2 clock in F269 and each instruction stage starts at 0 phase of this fosc/2 clock.
Who know the details of instrcution execution corresponding to fosc phase?
[ This message was edited by: xuyinghui on 02-08-2003 08:30 ]
