CMU - FMPLL clock reference values

[alessandro2]

Posted on July 19, 2017 at 10:02

Hello everyone,

I'm working with SPC56EL60L3 and SPC5Studio v5.0.

I'm not sure I get how does the CMU_0 FMPLL clock monitoring work.

Reading the user manual (RM0032) at page 277 13.3.3 and 13.3.4, I've found some details on the CMU_HFREFR_A and CMU_LFREFR_A registers, but I have some questions.

First question: when is the FMPLL clock checked? Whwnever I start the CMU by setting the SFM bit in the CSR register?

Second question:

Table 90 says: These bits determine the high reference value for the FMPLL clock. The reference value is given by: (HFREF_A÷16) × (FIRCOSC_CLK÷4). 

Table 90 says: 

These bits determine the low reference value for the FMPLL clock. The reference value is given by: (LFREF_A÷16) × (FIRCOSC_CLK÷4).

HFREF and LFREF are the contents of the two register, but what is FIRCOSC_CLK? Is it a predefined value or the content of a register, or what?

Thank you.

Regards

Alessandro

[Erwan YVIN · Accepted solution]

Posted on August 09, 2017 at 16:46

Hello Alessandro ,

Do not hesitate to use the Clocktree wizard (cf screenshot) relative to

SPC56EL60L3 (cf RLA Application)

FIRCOSC_CLK is 

The internal RC oscillator

it has a nominal frequency of 16 MHz.

The predefined value should be the reset values (cf below)

      Best Regards

                  Erwan