Summary
This article represents Part 1 of a two-part series addressing methods in which to minimize the effects of external component noise and interference on the STM32WB and STM32WL series of devices. Part 1 will focus on the devices and circuits typically present on a wireless board design and their potential impact on the overall RF output if not properly managed.
Part II will discuss the impact of the various degradation processes and provide guidance, with initial board layout, troubleshooting and resolving the problem at hand.Article Structure
, which provide noise floor sensitivity at or better than specifications.
Typically, these devices are just one of many functions on a PCB design and while the wireless devices perform extremely well in a stand alone situation, it is important to understand the impact external devices may have on wireless performance in general.
The degradation, is typically conducted, may present in the form of external power supply characteristics such as a switched mode power supply (SMPS). The impact that switching frequency and peak voltage variation may have on the wireless device needs to be considered. As PCB’s become smaller and smaller, defining a true effective ground plane becomes more difficult. It is therefore, necessary to understand the impact that such a design may have on a wireless device.
Degradation effects are normally observed in the form of noise entering the power supply terminals and ultimately appearing within the modulation/demodulation circuitry or, directly at RF. In the narrowband case, this impairment in the form of phase noise and discrete spurious tones that impact the of the overall spectrum of the transmitted signal and sensitivity of the received signal. On a wide band scenario, the impact may be in the form of a shifted noise floor and the spreading of spurious in a bandwidth much wider than the modulation bandwidth of interest.
These degradation effects not only impact performance but in turn, impact product certification.
This presentation addresses the main noise sources present on a PCB and the potential impact on the wireless system performance.
Figure 1 presents the noise model of a typical wireless device and the components that may be present on the same PCB design.
Figure 1: Simplified PCB Model
Driving the wireless device with an external SMPS is viable however, the characteristics of this external supply must be well understood and carefully chosen to not affect the operating characteristics of the wireless MCU. As the SMPS exhibits both a switching frequency component and peak charge/discharge component, both characteristics are required to be considered.
The presence of other digital devices must also be addressed as these devices may potentially introduce additional noise and spurious degradations. Devices with fast clock edges not only impact the power supply characteristics by demanding peak current within a short time interval, but an improperly designed return path and decoupling strategy, can also impact the noise floor of the system through internal ground currents.
The characteristics of the XTAL interfacing to the internal oscillator circuitry or, external oscillator, can impose system degradation effects if improperly selected. Degradation affecting spectral compliance, system signal to noise degradation and the introduction of spurious elements that mix directly into the radio spectrum, may all be possible. The degradations observed may be in the form of phase noise or drift. The resulting effect is observed as loss of range and sensitivity.
Finally, the ground plane is one of the most important items to consider. As PCB’s become smaller, more tightly packed, it becomes difficult to design an effective ground plane structure. Separate digital and analog ground planes, while a good concept, can serve as a capacitive coupling mechanisms facilitating the presence of unwanted energy. The reason for this is that these ground planes may combine to form a tuned or reactive circuit that does not necessarily attenuate frequency components over the desired frequency spectrum.
The above mechanisms, may combine to affect certification and meet regulatory standards. In the next section, a detailed view of how these mechanisms couple into the devices is presented.
Various system degradation effects are summarized in this section.
Phase noise is a parameter directly impacting the digital clock structure and RF phase locked loop structure of the device. Phase noise may be modelled in both the time domain and frequency domain. In the time domain, the resulting degradation is observed as jitter with a defined variance, while in the frequency domain, the degradation is observed as a nonlinear noise element, degrading the system signal to noise ratio within the modulation bandwidth of interest.
All oscillators and all Phase Locked Loop systems introduce and possess phase noise. The question is to determine how much phase noise can be tolerated. The device data sheet specification for the 32 MHz XTAL, is provided for compliance purposes. These specifications summarize the requirements of the XTAL to achieve the published parameters, in a standalone, test board situation.
It is not within the scope of this document to introduce a detailed tutorial on phase noise however, a straightforward summary of the concept, how it embeds itself within the system and its effects is provided. A typical XTAL oscillator exhibits the single sided frequency response as shown in Figure 2. The various slopes of the characteristic are typical of a XTAL phase noise characteristic. This response contributes a nonlinear noise term to the overall system signal to noise ratio, within a particular bandwidth.
Figure 2: XTAL Oscillator Baseband Single Sided Frequency Representation
Combined with a linear integer N or fractional N phase locked loop, a CW RF signal would display a noise characteristic as shown in Figure 3 (A). This characteristic is normal, and the contribution of the additional noise is taken into account within the system signal to noise requirements. However, a poorly chosen XTAL or, an on board noise source which modulates the XTAL oscillator, may combine to degrade the system received noise floor as shown in Figure 3 (B). In addition, if the reference XTAL oscillator or external noise element introduce defined spurious frequency components, then, these may appear at the overall RF CW output as distinct spurious frequency lines. This is also shown in Figure 3 (B). The roll off of the spectrum represents the RF phase locked loop bandwidth and not the modulation bandwidth.
Figure 3: Phase Noise Output at RF CW
The overall signal to noise or carrier to noise degradation is provided by:
In order to determine the exact signal to noise degradation, it is required to integrate the total contribution of the noise sources within the required bandwidth of interest, including the spurious elements.
In FSK systems, it is normal to modulate outside of RF loop bandwidth however, the increased phase noise or spurious, combine to affect the tracking properties of the RF local oscillator. The instability effect translates directly to the detector and thus, cannot be ignored as it impacts low signal to noise operation.
One of the major contributors to unwanted noise and spurious is typically due to a switched mode power supply. While the wireless devices described within this document, provide the capability to operate with an internal switched mode power supply (SMPS) configuration, the parameters of the SMPS are carefully determined to not degrade link parameters such as SNR.
Briefly described in Figure 1, a typical SMPS, typically which may be either a step down, buck boost, or boost converter. These devices, generate a switching frequency and peak ripple as part of their normal operational characteristic. The effect of this operational characteristic is the introduction of degradation effects. Such degradation effects may resemble that shown in Figure 3(B) in the form of an increased noise floor and the introduction of spurious that may couple directly into the signal modulation.
A typical switched mode power supply output is shown in Figure 4. Note that the power supply output contains low frequency and high frequency switching elements along with voltage ripple variation. The spectral effect of this power supply is also shown in Figure 4. Note the close in modulating distortion that is occurring. While this is a mild case, all these items, if not properly addressed will contribute to degrade the RF spectrum of the radio. In this case, the close in modulating tones may introduce a low frequency modulation within the carrier frequency local oscillator. The impact is reduced detection capability within the demodulator circuitry.
Figure 4: SMPS Time Switching Waveform and Impact on RF CW
Ground plane effects are effectively analyzed and demonstrated using an electromagnetic circuit simulator such as CST or ADS.
In this example to be presented, a cross section of a STM32WL circuit, output stage, has been isolated. The extracted cross section of the PCB represents a four-layer design with 50 ohm input and output terminations. The extraction has been done to demonstrate the effects of ground islands between layers. While the planes are connected through Vias, to ensure ground and Vdd continuity, the mesh effect of this connection introduces unwanted outcomes during simulation.
Consider the top layer of the PCB cross section as shown in Figure 5. In this figure, the output filter stage from the device output power amplifier pin through to the RF Switch input pin has been isolated. This represents the 50 ohm input and 50 ohm output terminals for the purposes of extracting S21 parameters.
Figure 5: Top Layer of 4 Layer Cross Section Simulation Access Points
In Figure 6, the bottom layer of the PCB cross section is shown. Note here that the ground plane is dissected by a power supply, Vdd, line however, the bottom ground plane area is still connected to the top plane, and ground islands in layer 2 and layer 3, through vias.
Figure 6: Bottom Layer of 4 Layer Cross Section (Ground Break Area)
The S21 sweep of the circuit as shown in Figure 5 and Figure 6 is shown in Figure 7. The expected result was to represent a flat, low pass filter response, with cut off approximately in the frequency region of 1 GHz. However, the distortion is due to the many ground islands and vias acting as reactive elements rather than true ground returns. As the simulation is mesh based, the currents have no choice but to flow through the vias and the ground islands. While this is an extreme example, it does represent what could occur with poor plane planning and routing. The expected result is shown in Figure 8.
Figure 7: Simulated Response with Multiple Ground Sectors and Vias
Figure 8: Ideal Expected Output
In Part I of this document, the key performance characteristics of wireless devices requiring careful design attention has been presented. The various devices present on PCB designs that contribute to performance degradation have also been discussed. Finally, addressing plane layout and its importance was presented.
In Part II of this document series, the effects of power supply noise and PCB layout and decoupling are presented in more detail.
- Overview
, which provide noise floor sensitivity at or better than specifications.Typically, these devices are just one of many functions on a PCB design and while the wireless devices perform extremely well in a stand alone situation, it is important to understand the impact external devices may have on wireless performance in general.
The degradation, is typically conducted, may present in the form of external power supply characteristics such as a switched mode power supply (SMPS). The impact that switching frequency and peak voltage variation may have on the wireless device needs to be considered. As PCB’s become smaller and smaller, defining a true effective ground plane becomes more difficult. It is therefore, necessary to understand the impact that such a design may have on a wireless device.
Degradation effects are normally observed in the form of noise entering the power supply terminals and ultimately appearing within the modulation/demodulation circuitry or, directly at RF. In the narrowband case, this impairment in the form of phase noise and discrete spurious tones that impact the of the overall spectrum of the transmitted signal and sensitivity of the received signal. On a wide band scenario, the impact may be in the form of a shifted noise floor and the spreading of spurious in a bandwidth much wider than the modulation bandwidth of interest.
These degradation effects not only impact performance but in turn, impact product certification.
This presentation addresses the main noise sources present on a PCB and the potential impact on the wireless system performance.
- Noise Model
Figure 1 presents the noise model of a typical wireless device and the components that may be present on the same PCB design.
Figure 1: Simplified PCB Model
Driving the wireless device with an external SMPS is viable however, the characteristics of this external supply must be well understood and carefully chosen to not affect the operating characteristics of the wireless MCU. As the SMPS exhibits both a switching frequency component and peak charge/discharge component, both characteristics are required to be considered.
The presence of other digital devices must also be addressed as these devices may potentially introduce additional noise and spurious degradations. Devices with fast clock edges not only impact the power supply characteristics by demanding peak current within a short time interval, but an improperly designed return path and decoupling strategy, can also impact the noise floor of the system through internal ground currents.
The characteristics of the XTAL interfacing to the internal oscillator circuitry or, external oscillator, can impose system degradation effects if improperly selected. Degradation affecting spectral compliance, system signal to noise degradation and the introduction of spurious elements that mix directly into the radio spectrum, may all be possible. The degradations observed may be in the form of phase noise or drift. The resulting effect is observed as loss of range and sensitivity.
Finally, the ground plane is one of the most important items to consider. As PCB’s become smaller, more tightly packed, it becomes difficult to design an effective ground plane structure. Separate digital and analog ground planes, while a good concept, can serve as a capacitive coupling mechanisms facilitating the presence of unwanted energy. The reason for this is that these ground planes may combine to form a tuned or reactive circuit that does not necessarily attenuate frequency components over the desired frequency spectrum.
The above mechanisms, may combine to affect certification and meet regulatory standards. In the next section, a detailed view of how these mechanisms couple into the devices is presented.
2.1 System Degradation Examples
Various system degradation effects are summarized in this section.
2.1.1 Phase Noise
Phase noise is a parameter directly impacting the digital clock structure and RF phase locked loop structure of the device. Phase noise may be modelled in both the time domain and frequency domain. In the time domain, the resulting degradation is observed as jitter with a defined variance, while in the frequency domain, the degradation is observed as a nonlinear noise element, degrading the system signal to noise ratio within the modulation bandwidth of interest.
All oscillators and all Phase Locked Loop systems introduce and possess phase noise. The question is to determine how much phase noise can be tolerated. The device data sheet specification for the 32 MHz XTAL, is provided for compliance purposes. These specifications summarize the requirements of the XTAL to achieve the published parameters, in a standalone, test board situation.
It is not within the scope of this document to introduce a detailed tutorial on phase noise however, a straightforward summary of the concept, how it embeds itself within the system and its effects is provided. A typical XTAL oscillator exhibits the single sided frequency response as shown in Figure 2. The various slopes of the characteristic are typical of a XTAL phase noise characteristic. This response contributes a nonlinear noise term to the overall system signal to noise ratio, within a particular bandwidth.
Figure 2: XTAL Oscillator Baseband Single Sided Frequency Representation
Combined with a linear integer N or fractional N phase locked loop, a CW RF signal would display a noise characteristic as shown in Figure 3 (A). This characteristic is normal, and the contribution of the additional noise is taken into account within the system signal to noise requirements. However, a poorly chosen XTAL or, an on board noise source which modulates the XTAL oscillator, may combine to degrade the system received noise floor as shown in Figure 3 (B). In addition, if the reference XTAL oscillator or external noise element introduce defined spurious frequency components, then, these may appear at the overall RF CW output as distinct spurious frequency lines. This is also shown in Figure 3 (B). The roll off of the spectrum represents the RF phase locked loop bandwidth and not the modulation bandwidth.
Figure 3: Phase Noise Output at RF CW
The overall signal to noise or carrier to noise degradation is provided by:
In order to determine the exact signal to noise degradation, it is required to integrate the total contribution of the noise sources within the required bandwidth of interest, including the spurious elements.
In FSK systems, it is normal to modulate outside of RF loop bandwidth however, the increased phase noise or spurious, combine to affect the tracking properties of the RF local oscillator. The instability effect translates directly to the detector and thus, cannot be ignored as it impacts low signal to noise operation.
2.1.2 Switching Power Supply
One of the major contributors to unwanted noise and spurious is typically due to a switched mode power supply. While the wireless devices described within this document, provide the capability to operate with an internal switched mode power supply (SMPS) configuration, the parameters of the SMPS are carefully determined to not degrade link parameters such as SNR.
Briefly described in Figure 1, a typical SMPS, typically which may be either a step down, buck boost, or boost converter. These devices, generate a switching frequency and peak ripple as part of their normal operational characteristic. The effect of this operational characteristic is the introduction of degradation effects. Such degradation effects may resemble that shown in Figure 3(B) in the form of an increased noise floor and the introduction of spurious that may couple directly into the signal modulation.
A typical switched mode power supply output is shown in Figure 4. Note that the power supply output contains low frequency and high frequency switching elements along with voltage ripple variation. The spectral effect of this power supply is also shown in Figure 4. Note the close in modulating distortion that is occurring. While this is a mild case, all these items, if not properly addressed will contribute to degrade the RF spectrum of the radio. In this case, the close in modulating tones may introduce a low frequency modulation within the carrier frequency local oscillator. The impact is reduced detection capability within the demodulator circuitry.
Figure 4: SMPS Time Switching Waveform and Impact on RF CW
2.1.3 Ground Plane Effects
Ground plane effects are effectively analyzed and demonstrated using an electromagnetic circuit simulator such as CST or ADS.
In this example to be presented, a cross section of a STM32WL circuit, output stage, has been isolated. The extracted cross section of the PCB represents a four-layer design with 50 ohm input and output terminations. The extraction has been done to demonstrate the effects of ground islands between layers. While the planes are connected through Vias, to ensure ground and Vdd continuity, the mesh effect of this connection introduces unwanted outcomes during simulation.
Consider the top layer of the PCB cross section as shown in Figure 5. In this figure, the output filter stage from the device output power amplifier pin through to the RF Switch input pin has been isolated. This represents the 50 ohm input and 50 ohm output terminals for the purposes of extracting S21 parameters.
Figure 5: Top Layer of 4 Layer Cross Section Simulation Access Points
In Figure 6, the bottom layer of the PCB cross section is shown. Note here that the ground plane is dissected by a power supply, Vdd, line however, the bottom ground plane area is still connected to the top plane, and ground islands in layer 2 and layer 3, through vias.
Figure 6: Bottom Layer of 4 Layer Cross Section (Ground Break Area)
The S21 sweep of the circuit as shown in Figure 5 and Figure 6 is shown in Figure 7. The expected result was to represent a flat, low pass filter response, with cut off approximately in the frequency region of 1 GHz. However, the distortion is due to the many ground islands and vias acting as reactive elements rather than true ground returns. As the simulation is mesh based, the currents have no choice but to flow through the vias and the ground islands. While this is an extreme example, it does represent what could occur with poor plane planning and routing. The expected result is shown in Figure 8.
Figure 7: Simulated Response with Multiple Ground Sectors and Vias
Figure 8: Ideal Expected Output
- Summary
In Part I of this document, the key performance characteristics of wireless devices requiring careful design attention has been presented. The various devices present on PCB designs that contribute to performance degradation have also been discussed. Finally, addressing plane layout and its importance was presented.
In Part II of this document series, the effects of power supply noise and PCB layout and decoupling are presented in more detail.
