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Question about link script for SPC58EC80 with SPC5Studio.

otcagon
Associate II

Hello,

 

I am currently using SPC58EC80 with SPC5Studio.

I have some problem to load the data located in ROM area to RAM area when boot.

 

I am using " > CAL_RAM AT > CAL_ROM" command for loading the data from 0x013A0000 to 0x400B0000.

I check the RAM area after booting the SPC58EC80 but no data are loaded from 0x400B0000.

 

If anyone try to success to load the data when booting with link scrpit, please guide me.

I also write down rom.c contents at the end.

 

Here is contents of link script and its name is user.ld. I delete application.ld file on purpose.

MEMORY
{
   
    flash (rx)             : org = 0x00FC0000, len = 4M - 128k   
   CAL_ROM (rx)    : org = 0x013A0000, len = 128k
 
    MEA_RAM (rxw)   : org = 0x400A8000, len = 32k
    CAL_RAM (rxw)   : org = 0x400B0000, len = 128k
    ram (rxw)              : org = 0x400D0000, len = 224k
 
    dram0 (rxw)          : org = 0x50800000, len = 64k
    dram2 (rxw)          : org = 0x52800000, len = 64k
}
 
ENTRY(_reset_address2)
 
/*
 * Derived constants.
 */
__flash_size__          = LENGTH(flash);
__flash_start__         = ORIGIN(flash);
__flash_end__           = ORIGIN(flash) + LENGTH(flash);
 
__ram_size__            = LENGTH(ram);
__ram_start__           = ORIGIN(ram);
__ram_end__             = ORIGIN(ram) + LENGTH(ram);
 
__dram0_size__          = LENGTH(dram0);
__dram0_start__         = ORIGIN(dram0);
__dram0_end__           = ORIGIN(dram0) + LENGTH(dram0);
 
__dram2_size__          = LENGTH(dram2);
__dram2_start__         = ORIGIN(dram2);
__dram2_end__           = ORIGIN(dram2) + LENGTH(dram2);
 
__CAL_ROM_size__        = LENGTH(CAL_ROM);
__CAL_ROM_start__       = ORIGIN(CAL_ROM);
__CAL_ROM_end__         = ORIGIN(CAL_ROM) + LENGTH(CAL_ROM);
 
__CAL_RAM_size__        = LENGTH(CAL_RAM);
__CAL_RAM_start__       = ORIGIN(CAL_RAM);
__CAL_RAM_end__         = ORIGIN(CAL_RAM) + LENGTH(CAL_RAM);
 
__MEA_RAM_size__        = LENGTH(MEA_RAM);
__MEA_RAM_start__       = ORIGIN(MEA_RAM);
__MEA_RAM_end__         = ORIGIN(MEA_RAM) + LENGTH(MEA_RAM);
 
SECTIONS
{
    . = ORIGIN(flash);
    .boot0 : ALIGN(16) SUBALIGN(16)
    {
        KEEP(*(.boot))
        KEEP(*(.handlers))
        KEEP(*(.crt0))
    } > flash
 
    .boot1 : ALIGN(16) SUBALIGN(16)
    {
        /* The IVPR registers require a 256 bytes alignment.*/
        . = ALIGN(0x100);
        __ivpr0_base__ = .;
        KEEP(*(.core0_ivors))
 
        /* The IVPR registers require a 256 bytes alignment.*/
        . = ALIGN(0x100);
        __ivpr2_base__ = .;
        KEEP(*(.core2_ivors))
 
        /* The vectors table requires a 4kB alignment.*/
        . = ALIGN(0x1000);
        KEEP(*(.vectors))
    } > flash
 
/* .caldata section contains the data, assumed to be in CAL_ROM */
.caldata :
{
       . = ALIGN(4);     
        *(.caldata)
       . = ALIGN(4);
} > CAL_RAM AT > CAL_ROM
.....
 
rom.c file contents
__attribute__((section(".caldata"))) uint16_t
NCV7720_AH_INIT = 0xFFFF,
NCV7720_AL_INIT = 0xBFFF,
NCV7720_BH_INIT = 0xFFFF,
NCV7720_BL_INIT = 0xBFFF,
NCV7720_AH_DATA = 0x7FFF,
NCV7720_AL_DATA = 0x3FFF,
NCV7720_BH_DATA = 0x7FFF,
NCV7720_BL_DATA = 0x3FFF;
 
 
 
 
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