Observing strange voltage ramp when VDD is above 2V - LSM6SOTR

[OLewi.1]

We've just changed the way our system is powered: Previously the accelerometer was powered from a 1.8V regulator, now it's powered directly from a 3V coin cell (schematic part attached).

With the change, we have started to observe a strange ramping which is visible from about 2V upwards and increases with an increase in VDD. Attached is an image of the current ramping, with VDD set to approx 2.9V. The larger thin spikes belong to a BLE module, the very tiny spikes are all I would expect to see of the accelerometer in operation - in fact that is the case when running at 1.8V.

The accelerometer is configured to capture in FIFO mode, the gyro is off. The IRQ is used to notify FIFO events and to flush the buffer. Same ramp is visible, regardless of power mode (ultra low, normal, high-perf). We are only ever capturing at 12.5Hz. No extended functionality is enabled (motion event, etc).

We use SPI Mode 1 to communicate with the device, both IRQ pins are connected to our Micro.

Is this expected behavior?

Thanks.

[Eleon BORLINI]

Hi @OLewi.1​ ,

It is a strange (and unpredicted) behavior. Did you have the possibility to test another part, in the same circuit?

Another possibility is that the 3V coin cell is not capable of providing to the LSM6DSO enough current to manage the peak current of the device during SPI communication (this is strange indeed). Which is the current capability of your battery?

-Eleon

[OLewi.1 · Accepted solution]

Hi Eleon, and thanks for your reply.

After a few days with a scope I figured it out: It turns out the SPI data lines were left floating in-between toggling the CS - this was the cause of the funny ramp. The solution was simple, when CS is idle, change the SPI pins (MOSI, MISO & CLK) to GPIOs and drive them low. Then whenever I need to access the accelerometer, change those pins back to SPI mode just before switching CS.

Strange that this phenomenon was never visible when the accelerometer was powered from 1.8V????

[Eleon BORLINI]

Great @OLewi.1​ ! Glad you found the solution.

I'm wondering if, for Vdd = 1.8V, the CS was automatically recognized in low state from either the chip or the microcontroller, while for higher Vdd the CS state was undefined (and not automatically recognized as low digital state).

-Eleon

[OLewi.1]

That would really surprise me. Vdd is common across parts and is always the logic level for all digital I/O - that was the same with and without the regulator. I would expect the digital switch level to change automatically as Vdd changes. CS is also required to terminate any commands to the accelerometer, so I'm assuming that it was toggling.

In any case, now it's working I'm not going to loose any more sleep over it. Thanks again Eleon.