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LSM6DS3 FTH or FIFO_FULL flags used as ISR

L77d
Associate II

Hi,

I am using steval MKI160V1 coupled with pybv1.0 under microphyton (spi speed 525000bits/s).

I'd like to get every samples from gyro and accel at 1666 hertz speed using interruption.

I have configured lsm6ds3( whoami = 69h) to do so, but while I am flushing every samples reading fifo_status1 n 2 registers to know the entire of unread words in fifo, there sometimes a "rebound like" of interruption coming next to the previous one !

Why is the documentation saying (page 31/112 5.4.3. continuous mode) that it is possible to route FIFO_STATUS2 (3Bh) (FTH) to the INT1 pin by writing in register INT1_CTRL (0Dh) (INT1_FTH) = ‘1

FIFO_STATUS2 is only one byte long while FTH can contain size of 2^12 words of data ?

I am not sure of the correct use of FTH neither interruption for this project ?

To have a better look at what appends I have reduced odr to 26hertz...

Thx for your help

 

 

 

I have set INT2 to be active if Fifo is full.

When Py Board line rise the irq then I decide to read FIFO Status Registers to know how much data are available in FIFO...that might be 0 and flags of fifo full set but absolutly not !!!

INT2 rises while registers says that there are 3836 words in FIFO and FIFO_STATUS2 (3Bh) most quartet is 10d so that FTH bit and FIFO_FULL bit are sets !!!!!

How is that possible ?

2 REPLIES 2
Federica Bossi
ST Employee

Hi @L77d ,

Welcome to ST Community!

 

I think you're referring to the datasheet, please, take a look at the application note, paragraph 8.2.3.

It may give you more insight on how to configure the FIFO. 

If you still have issues, could you please send the configuration like so?

address = data 

i.e.

10h = 0ah?

It would make it easier to understand your exact configuration.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
L77d
Associate II

Thx for your reply

I have since turned around that problem, when FTH rises on INT1, I decided to flush the exact value "FTH" of words contained in FIFO no matter how much there are in the FIFO neither how much I have left behind....

So no FIFO full interrupt happen then....

But I get another problem that I related in another post....

https://community.st.com/t5/mems-sensors/lsm6ds3-fifo/td-p/628746