LSM6DS3 EVB "STEVAL-MKI160V1" communication issue using SPI 4 wire

[SChin.2]

Hello ST

here am using STEVAL-MKI160V1 in which LSM6DS3 is placed and an trying communicate with it over SPI.

Physical connections:

• CS- CS
• SCL- CLK
• SDA - SDO of mc
• SDO - SDI of mc
• VDD - 3.3V
• GND - GND

SPI Configuration:

• SPI Freq- 1MHZ
• Slave Select - Active low
• Clock Phase - Read on ODD edge
• clock polarity - Active High
• bit order - MSB first

Am sending command "0x8F00"(WHO AM I-0F) over MOSI line and am not able to see response "0x0069" instead am seeing 0x0B00/0x0F00/0x0000 etc.. which is not consistent, I believe all the responses are wrong. Do I missing something in Physical connections or doing something wrong in SPI config ?. please help me

Seen VDDIO voltage level is 5V with out having any connection on it , but still VDDIO max is 3.7 as per data sheet , is that the issue ?

Do I need to make any additional connections or circuit on OCS/SCx/SDx/OSDO ??

Please do the needfull.

[Eleon BORLINI]

Hi @SChin.2​ ,

>> Seen VDDIO voltage level is 5V with out having any connection on it, but still VDDIO max is 3.7 as per data sheet, is that the issue?

Yes, this could be the issue, both in the case that Vdd = VddIO = 5V or Vdd < VddIO = 5V. In the former case, the most probable SPI MISO data you are likely to receive are 0xFF patterns, while in the latter case you might receive data different from 0xFF, since the Vdd is valid, but inconsistent since the internal digital logic of the sensor will not recognize the High / Low levels. Almost all the ST sensors are CMOS 3.3V and below logic compatible.

Please note also that you could be in an out-of-absolute-maximum ratings condition described in the datasheet, p.27, i.e. 4.8V.

Can you try lowering the VddIO and see what happens (if the part is not yet damaged)?

-Eleon

[SChin.2]

Hello @Eleon BORLINI​ 

Thanks for the quick response !

How to lower the voltage on VDDIO, since here I just connected 3.3V to VDD and GND to GND ?

Is VDDIO is input or output ?

[Eleon BORLINI]

Hi @SChin.2​ ,

VddIO is an input and determines the high and low level of the sensor digital output. One possibility is to tie it to Vdd, so that it will be equal to 3.3V and there will be no inconsistency in detecting the digital levels.

You are using SPI so no need of external pull-ups to VddIO.

-Eleon

[SChin.2]

Hello @Eleon BORLINI​ 

After shorting VDD & VDDIO , I mean after supplying 3.3V to VDDIO am seeing 4.2V on both VDD and VDDIO. Is this a good or bad sign ?

[Eleon BORLINI]

It means that there is a residual connection or a resistance partition between VddIO and probably the previous 5V supply...

Could you share the schematic to check it?

-Eleon

[SChin.2]

I don't have the Schematic of the EVB

FYI am using this

https://www.st.com/content/ccc/resource/technical/document/data_brief/0b/f5/7b/e2/d2/fe/44/75/DM00164425.pdf/files/DM00164425.pdf/jcr:content/translations/en.DM00164425.pdf

if available can you please share the schematic of the EVB.

[Eleon BORLINI]

The schematic of that board (STEVAL-MKI160V1) is in the second page of the link you shared...

I'm now understanding from where the 5V comes... it should come from your power supply tree, the is external to the eval board (probably coming from your custom motherboard...)

-Eleon

[SChin.2]

Hello @Eleon BORLINI​ 

If I have alone two wires GND to GND and 3.3V to VDDIO & VDD then am seeing 3.3V at VDDIO & VDD.. but if I connect all the SPI lines then am seeing 4.2V..

Why SPI lines making this issue ?

[Eleon BORLINI]

Are you maybe connecting the device (any lines other than Vdd/VddIO, such as CS, SPI lines...) to an application processor compatible with 5V logic?

-Eleon