Does the INTERNAL_FREQ_FINE register of ASM330LHH indicate that there is a frequency deviation? In this case, how should it be used under the standard time interval algorithm requirements?

[wb.2]

Hello, may I ask whether the INTERNAL_FREQ_FINE register was written before delivery?Can it be understood that the actual data frequency of each ASM330LHH IC is different?

My project will use many same sensors to collect acceleration and gyroscope at the same time, and the algorithm requires standard, fixed data intervals. When I used FIFO and timestamp of ASM330HHL to get each data from SPI, I found that the actual data and time obtained cannot exactly correspond to the time in the real world.

What should I do, please?

Thanks very much.

[Eleon BORLINI]

Hi @wb.2​ ,

the INTERNAL_FREQ_FINE (63h) register is a read-only register (as you can see from the datasheet p.69), so it is calibrated at production level. The ODR is not always exactly the nominal one because of the production spread of the process that defines the ASIC internal clock tree. Suppose you have a number (e.g.10) different ASM330LHH devices: after their common initialization, you should calculate the minimum ODR among the sensors with the formula in p.69 of the datasheet:

• ODR_Actual = (6667 + ((0.0015 * INTERNAL_FREQ_FINE) * 6667)) / ODR_Coeff

Setting the BDU bit of CTRL3_C (12h) register you can be sure that the data doesn't update until the next reading / data available: you'll be now able to run readings at the minimum ODR among sensors (e.g. via SPI, parallel lines), collecting the outputs of the data at the same time.

Regards

[Eleon BORLINI]

Hello @wb.2​ ,

was the above answer helpful for you?

-Eleon

[Shannon Pahl]

Is there a way to calculate the actual ODR for accelerometers that don't have this register? e.g. on the lis2ds12, time how long it takes for x data read signals ?

[Eleon BORLINI]

Hi @Shannon Pahl​ ,

I suggest you to post a new question on the community, to get more visibility 😉

The common way to measure the true ODR is to enable the data ready (in the LIS2DS12 case, write "1" on the INT1_DRDY bit of CTRL4 (23h) register) and count the number of times the INT1 pin toggles in 1 second.

-Eleon