When I read the FIFO with SPI the SDO pin is sometimes left LOW. This causes a current leak through the internal pull-up. See pic attached showing 1 minute of readings every 800ms. As you can see the current is high every time the SDO pin is low. I assume the internal pull-up is causing the current.
I've read the data sheet and the application note AN5326 but I cannot see why this happens.
I'm using ODR 25HZ with Power mode 4, +2G range and continuous FIFO. SPI 4-wire. NRF52840. I have tested the NRF52840 current draw and determined that the accelerometer is drawing the current.
To hack it lower before sleeping, I've set -1 (oxFF) to my Z_OFS_REG and I read from the Y_OFS_REG (this register precedes Z_OFS_REG). This results in the trailing SDO bit always being high at the end of the SPI read. This leaves the SDO line HIGH which avoids the problem. I would like to know if there's a more conventional way of fixing this.
I've tried all 4 SPI modes and I've tried SPI frequencies 125khz, 4Mhz and 8Mhz.
My accelerometer is the STEVAL-MKI206V1 breadboarded with an nrf52840 dongle. 4 wires from accelerometer to dongle. no additional components.
Any help is greatly appreciated.
