All,
I'm working on the basics of getting the SPI communication set up for the L9780 IC and am running into some issues, so I'd appreciate some feedback or a double-check. It appears so far that I'm able to send a command via the control word and successfully echo that back when the REG=1 bit is set. When doing so, the CB bits are correct, so everything seems to be functioning as intended.
My issue is that I'm getting a SPI fault when REG=0 to get the status register as an output. The CB[1,0] bits are correct, however SPIF1 is asserted. The datasheet has a few sections on this so I'll address each of them:
- 5.5.1 SPI data fault
- Datasheet says this is set when the CB[1,0] bits are not set as expected.
- My base control word is 0x00040F18192A8040 which appears to be OK.
- When enabling VCCS and INRC, byte 14 and 13 get updated so the word is 0x02040F.... and 0x0244F.... respectively.
- Additionally when getting my "echo" of the SI register, the control word is 0x0A440F18192A8040 which also appears to be OK.
- 5.5.2 SPI length fault
- Datasheet states that SPIF1 is asserted when receiving an SPI frame with a length different from [64 + (n*8)] bits
- This one I'm not 100% sure on with respect to the (n*8) term. Is this applicable only if running the L9780 in a "Daisy chain" configuration where more than one 64b word gets sent in a SPI frame? Basically, is it just stating that the reg is expecting to get byte width communication over SPI? So if the CSN was asserted or a clock pulse was given such that 7bits or 9bits were received, then the length fault would occur?
- 5.5.3 Invalid command fault
- SPIF1 asserted if one of the 4 command conflicts listed occur
- This one also appears to be OK. Per the datasheet and the control word I listed above, it looks like I'm ok. The only part I have a question on is conditions 3 and 4; It states for 3 that when VCCS is enabled, that SPIF1 is asserted if the frame modifies VCCSOUT, COMPSEL, or VCCSCAP[x] bits. This should only happen on these bits being changed, correct? Continuing to send the control word I started with should not be changing these bits from their previous state, so am I correct in my understanding that this should not be triggered?
The last thing I really need to do is get a logic analyzer on the SPI lines and verify that what I'm seeing in my FW is what's really being transmitted. As mentioned above, I'm able to echo-back the same word that I'm sending but if its a "two wrongs make a right" situation something could still be incorrect.
Appreciate the time, thanks!
