Input and output voltage range of ULN2065B (negative) ULN2065B�?�入力�?出力電圧範囲（負）

[RKiku.1]

Negative voltage undershoot on input and output of ULN2065B. How many negative voltages can the input and output tolerate?

If possible, I would like to get support from Japanese staff.

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[Peter BENSCH]

Welcome, @RKiku.1​, to the community!

The community relies primarily on mutual help between users (see About Community, General Use).

In addition to the community, you can also get personal support via Online Support OLS, alternatively you can contact your local distributor or the nearest ST office.

Anyway, the ULN2065B is a bipolar transistor array that has a parasitic pn junction at its inputs, as can also be seen in the data sheet, fig. 1. For this reason, the designer must ensure that the negative input voltage remains below the forward voltage of silicon pn junctions, which can be achieved with an anti-parallel Schottky diode, for example.

A negative voltage at the outputs would operate the respective transistor pair in reverse bias mode, which is not specified and must be avoided.

However, according to the data sheet, no value is guaranteed for both cases, which is why suitable external protective measures must then be taken, depending on the particular application.

Does it answer your question?

Regards

/Peter

[RKiku.1]

Thank you for your answer.

I understand how to use the community.

(My apologies for being so uninformed.)

Regarding the ULN2065B, in summary, am I correct in understanding that neither input nor output can be guaranteed by the manufacturer to produce a negative voltage even for a short time (about 50 ns at the output terminals in our case)?

I also inserted a Schottky diode to clamp the negative undershoot on the input and output.

But it is inevitable that a negative voltage will be generated for the forward voltage of the Schottky diode.

Therefore, I was asking how many negative voltages the input and output can tolerate.

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[Peter BENSCH · Accepted solution]

Of course, a negative voltage equal to the forward voltage is dropped at the Schottky diode if it is at the input, for example, and a negative input voltage is present there. However, this is not a problem both at the input and at the output, as this forward voltage is typically well below the threshold voltage of the silicon pn junctions.

The maximum tolerable voltage depends on the current limitation before the Schottky diode, since the current must be limited either by the output resistance of the voltage source or by a discrete resistor.

As for short pulses, like the 50ns you mentioned at the output terminals, it depends on the effective voltage level of the pulses. If it is below the threshold voltage of the silicon pn junctions due to external Schottky diodes, there is no problem. If it is above, the behaviour is not defined, so this condition must be avoided.

Regards

/Peter

[RKiku.1]

Input undershoot was solved by using a standard logic IC.

(Negative voltage is no longer generated.)

The output undershoot can be clamped to about -0.14V by inserting a Schottky diode.

This is below the threshold voltage (0.55V) of the Schottky diode used, so I have determined that there is no problem.

Thank you very much for your answer.

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