Hi Winfred,
I found more information on this topic in the documentation of the chip:
1) There is a small difference between SLEEP and STANDBY state: in sleep state slow clock is running but in standby it is not
2) Watchdog is clocked by this slow clock
3) Watchdog RST line is connected to a gate as equivalent input to BLE RSTs line, while BLE RST can be activated by RESET pin.
These are only observations and conclusions from the documentation, and I did not verified it in circut, but:
a) if RESET pin can wake up the chip, it does it by BLE RSTs line
b) BLE RSTs line and WDG RST are symetric input of the gate, so WDG RST can reset the chip as well
c) Watchdog is clocked from slow clock that is running in SLEEP state
Does it mean that watchdog can wake up the chip from SLEEP state?
Regards,
Piotr Romaniuk
