hello community,
I´m using PB10/PB11 as I2C1 and PB6/PB7 as I2C2.
I2C1 works correctly.
But I2C2 not, after reset on PB6 and PB7 I just get some messy signals as below, It seems the I2C2 is not initialized with succcess.
Actually the both I2C are initialized in the same way:
Here is the pin definition for both I2C
//sensor1
#define BSP_I2C I2C1
#define BSP_I2C_CLK_ENABLE() LL_APB1_EnableClock(LL_APB1_PERIPH_I2C1)
#define BSP_I2C_CLK_DISABLE() LL_APB1_DisableClock(LL_APB1_PERIPH_I2C1)
#define BSP_I2C_DATA_PIN LL_GPIO_PIN_10
#define BSP_I2C_DATA_GPIO_PORT GPIOB
#define BSP_I2C_DATA_GPIO_PULL LL_GPIO_PULL_NO
#define BSP_I2C_DATA_GPIO_AF() LL_GPIO_SetAFPin_8_15(GPIOB, LL_GPIO_PIN_10, LL_GPIO_AF_2)
#define BSP_I2C_DATA_GPIO_CLK_ENABLE() LL_AHB_EnableClock(LL_AHB_PERIPH_GPIOB)
#define BSP_I2C_DATA_GPIO_CLK_DISABLE() LL_AHB_DisableClock(LL_AHB_PERIPH_GPIOB)
#define BSP_I2C_CLK_PIN LL_GPIO_PIN_11
#define BSP_I2C_CLK_GPIO_PORT GPIOB
#define BSP_I2C_CLK_GPIO_PULL LL_GPIO_PULL_NO
#define BSP_I2C_CLK_GPIO_AF() LL_GPIO_SetAFPin_8_15(GPIOB, LL_GPIO_PIN_11, LL_GPIO_AF_2)
#define BSP_I2C_CLK_GPIO_CLK_ENABLE() LL_AHB_EnableClock(LL_AHB_PERIPH_GPIOB)
#define BSP_I2C_CLK_GPIO_CLK_DISABLE() LL_AHB_DisableClock(LL_AHB_PERIPH_GPIOB)
//sensor2
#define BSP_I2C2 I2C2
#define BSP_I2C2_CLK_ENABLE() LL_APB1_EnableClock(LL_APB1_PERIPH_I2C2)
#define BSP_I2C2_CLK_DISABLE() LL_APB1_DisableClock(LL_APB1_PERIPH_I2C2)
#define BSP_I2C2_DATA_PIN LL_GPIO_PIN_7
#define BSP_I2C2_DATA_GPIO_PORT GPIOB
#define BSP_I2C2_DATA_GPIO_PULL LL_GPIO_PULL_NO
#define BSP_I2C2_DATA_GPIO_AF() LL_GPIO_SetAFPin_0_7(GPIOB, LL_GPIO_PIN_7, LL_GPIO_AF_0)
#define BSP_I2C2_DATA_GPIO_CLK_ENABLE() LL_AHB_EnableClock(LL_AHB_PERIPH_GPIOB)
#define BSP_I2C2_DATA_GPIO_CLK_DISABLE() LL_AHB_DisableClock(LL_AHB_PERIPH_GPIOB)
#define BSP_I2C2_CLK_PIN LL_GPIO_PIN_6
#define BSP_I2C2_CLK_GPIO_PORT GPIOB
#define BSP_I2C2_CLK_GPIO_PULL LL_GPIO_PULL_NO
#define BSP_I2C2_CLK_GPIO_AF() LL_GPIO_SetAFPin_0_7(GPIOB, LL_GPIO_PIN_6, LL_GPIO_AF_0)
#define BSP_I2C2_CLK_GPIO_CLK_ENABLE() LL_AHB_EnableClock(LL_AHB_PERIPH_GPIOB)
#define BSP_I2C2_CLK_GPIO_CLK_DISABLE() LL_AHB_DisableClock(LL_AHB_PERIPH_GPIOB)
Here is the init function for both I2C
//sensor1
void BSP_I2C_Init(void)
{
/* Initialize the GPIOs associated to the I2C port */
BSP_I2C_DATA_GPIO_CLK_ENABLE();
LL_GPIO_SetPinMode(BSP_I2C_DATA_GPIO_PORT, BSP_I2C_DATA_PIN, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinSpeed(BSP_I2C_DATA_GPIO_PORT, BSP_I2C_DATA_PIN, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetPinOutputType(BSP_I2C_DATA_GPIO_PORT, BSP_I2C_DATA_PIN, LL_GPIO_OUTPUT_OPENDRAIN);
LL_GPIO_SetPinPull(BSP_I2C_DATA_GPIO_PORT, BSP_I2C_DATA_PIN, BSP_I2C_DATA_GPIO_PULL);
BSP_I2C_DATA_GPIO_AF();
BSP_I2C_CLK_GPIO_CLK_ENABLE();
LL_GPIO_SetPinMode(BSP_I2C_CLK_GPIO_PORT, BSP_I2C_CLK_PIN, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinSpeed(BSP_I2C_CLK_GPIO_PORT, BSP_I2C_CLK_PIN, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetPinOutputType(BSP_I2C_CLK_GPIO_PORT, BSP_I2C_CLK_PIN, LL_GPIO_OUTPUT_OPENDRAIN);
LL_GPIO_SetPinPull(BSP_I2C_CLK_GPIO_PORT, BSP_I2C_CLK_PIN, BSP_I2C_CLK_GPIO_PULL);
BSP_I2C_CLK_GPIO_AF();
/* Initialize the I2C clock */
BSP_I2C_CLK_ENABLE();
LL_I2C_Disable(BSP_I2C);
/* Configure the SDA setup, hold time and the SCL high, low period
* For Fast-mode 400 kHz, PRESC | 0h | SCLDEL | SDADEL | SCLH | SCLL
* 1h | 0h | 3h | 2h | 03h | 09h
*/
LL_I2C_SetTiming(BSP_I2C, 0x10320309);
/* Enable Clock stretching */
LL_I2C_EnableClockStretching(BSP_I2C);
/* Enable Peripheral in I2C mode */
LL_I2C_SetMode(BSP_I2C, LL_I2C_MODE_I2C);
/* Enable the I2C peripheral */
LL_I2C_Enable(BSP_I2C);
/* Enable I2C transfer complete/error interrupts:
* - Enable Receive Interrupt
* - Enable Not acknowledge received interrupt
* - Enable Error interrupts
* - Enable Stop interrupt
*/
// LL_I2C_EnableIT_TX(BSP_I2C);
// LL_I2C_EnableIT_RX(BSP_I2C);
// LL_I2C_EnableIT_TC(BSP_I2C);
// LL_I2C_EnableIT_NACK(BSP_I2C);
// LL_I2C_EnableIT_ERR(BSP_I2C);
// LL_I2C_EnableIT_STOP(BSP_I2C);
}
//sensor2
void BSP_I2C2_Init(void)
{
/* Initialize the GPIOs associated to the I2C port */
BSP_I2C2_DATA_GPIO_CLK_ENABLE();
LL_GPIO_SetPinMode(BSP_I2C2_DATA_GPIO_PORT, BSP_I2C2_DATA_PIN, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinSpeed(BSP_I2C2_DATA_GPIO_PORT, BSP_I2C2_DATA_PIN, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetPinOutputType(BSP_I2C2_DATA_GPIO_PORT, BSP_I2C2_DATA_PIN, LL_GPIO_OUTPUT_OPENDRAIN);
LL_GPIO_SetPinPull(BSP_I2C2_DATA_GPIO_PORT, BSP_I2C2_DATA_PIN, BSP_I2C2_DATA_GPIO_PULL);
BSP_I2C2_DATA_GPIO_AF();
BSP_I2C2_CLK_GPIO_CLK_ENABLE();
LL_GPIO_SetPinMode(BSP_I2C2_CLK_GPIO_PORT, BSP_I2C2_CLK_PIN, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinSpeed(BSP_I2C2_CLK_GPIO_PORT, BSP_I2C2_CLK_PIN, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetPinOutputType(BSP_I2C2_CLK_GPIO_PORT, BSP_I2C2_CLK_PIN, LL_GPIO_OUTPUT_OPENDRAIN);
LL_GPIO_SetPinPull(BSP_I2C2_CLK_GPIO_PORT, BSP_I2C2_CLK_PIN, BSP_I2C2_CLK_GPIO_PULL);
BSP_I2C2_CLK_GPIO_AF();
/* Initialize the I2C clock */
BSP_I2C2_CLK_ENABLE();
LL_I2C_Disable(BSP_I2C2);
/* Configure the SDA setup, hold time and the SCL high, low period
* For Fast-mode 400 kHz, PRESC | 0h | SCLDEL | SDADEL | SCLH | SCLL
* 1h | 0h | 3h | 2h | 03h | 09h
*/
LL_I2C_SetTiming(BSP_I2C2, 0x10320309);
/* Enable Clock stretching */
LL_I2C_EnableClockStretching(BSP_I2C2);
/* Enable Peripheral in I2C mode */
LL_I2C_SetMode(BSP_I2C2, LL_I2C_MODE_I2C);
/* Enable the I2C peripheral */
LL_I2C_Enable(BSP_I2C2);
/* Enable I2C transfer complete/error interrupts:
* - Enable Receive Interrupt
* - Enable Not acknowledge received interrupt
* - Enable Error interrupts
* - Enable Stop interrupt
*/
// LL_I2C_EnableIT_TX(BSP_I2C);
// LL_I2C_EnableIT_RX(BSP_I2C);
// LL_I2C_EnableIT_TC(BSP_I2C);
// LL_I2C_EnableIT_NACK(BSP_I2C);
// LL_I2C_EnableIT_ERR(BSP_I2C);
// LL_I2C_EnableIT_STOP(BSP_I2C);
}
***********************************************************************
any idea?
thanks in advance.
Danny
1 ACCEPTED SOLUTION
Accepted Solutions
Let´s make this question more simple, only I2C2(PB6/7) is not working
this is the pin definition:
this is my init function:
even the clock signal is not correct:
Hi Rene,
thanks for the reply!
I found this in the document RM0479 page 106:
Does it mean that the PB6/7 as I2C2 only support either standard mode or FM+? Fast mode at these pins are not supported. Because in my init function for I2C2 I just copied the timing setting from I2C1(PB10/11), which supports fast mode.
I do find this tools from ST and try to reproduce this settings, then change it to standard mode or FM+
If this is the reason, could you teach me how to set the parameters in the table correctly and firstly reproduce the timing setting for fastmode?
Hi Danny0007,
The Fast mode+ allows the I²C to operate at 1Mbit/s, compared to the standard mode and the fast mode speed which are 100kbit/s and 400kbit/s respectively. Both I²C1 and I²C2 support all these modes, but for FM+ on dedicated pins.
I2C I/Os supports 20 mA output current drive for fast-mode plus operation.
This is enabled by setting the driving capability control bits for SCL and SDA
in Section 8.2.3 I2C Fast-Mode Plus pin capability control register (I2C_FMP_CTRL).
The timings from I²C1 are based on a 16MHz I²C source clock and are given in the Reference Manual in the table 58
The clock for I²C1 and I²C2 is fixed and set to 16MHz (picture from RCC section, green line)
The PCLK is used for registers only (blue line, Figure 83 in Reference Manual).
So if you want to change the i²C mode, refer to table 58.
May I point you to an ST Tool (if you don't already know it) that will allow you to configure your MCU and which will generate code to initialize peripherals that you need (STM32CubeMX):
https://www.st.com/en/development-tools/stm32cubemx.html
This may help you to see if you missed something in your settings. This tool is also available in STM32CubeIDE if you use it for your developments.
Hope this can help you.
Kind Regards.
I´m using Wise-Studio, this is the output from debug console:
Open On-Chip Debugger 0.12.0-rc2+dev-00962-g12ce17094-dirty (2022-11-07-16:58)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
Info : tcl server disabled
Info : telnet server disabled
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 0254
Info : CMSIS-DAP: Serial# = 0720000197969908a5a5a5a505dbff333939505043087737
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : clock speed 1200 kHz
Info : SWD DPIDR 0x0bc11477
Info : [bluenrg-lp.cpu] Cortex-M0+ r0p1 processor detected
Info : [bluenrg-lp.cpu] target has 4 breakpoints, 2 watchpoints
Info : starting gdb server for bluenrg-lp.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
undefined debug reason 8 - target needs reset
[bluenrg-lp.cpu] halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1000177c msp: 0x20010000
[bluenrg-lp.cpu] halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1000177c msp: 0x20010000
Warn : keep_alive() was not invoked in the 1000 ms timelimit. GDB alive packet not sent! (2920 ms). Workaround: increase "set remotetimeout" in GDB
[bluenrg-lp.cpu] halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1000177c msp: 0x20010000
and the values in APB1ENR are unnormal:
Hi @Rene Lenerve
I see on page 16 table 6:
PB6/7 are opendrain in AF0, different from others... maybe need some special settings?
