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Anyone has a driver for QSPI flash S25FL512S?

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ST has something on their github but it is incomplete.

The Infineon/Cypress forum offers something here but it is too obtuse.

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Andreas BolschBest answer

Lead III

The S25FL512S is in no way special, a driver for e.g. S25FL128S will work, too (as far as reading status reg., read ID are concerned and even for read for the bottom half).

(The changes for 4-byte address mode are rather simple, e.g. change the command bytes accordingly and the ADSIZE field in QUADSPI_CCR, but that's the final step, when read ID etc. work.)

Probably the pin setup is not correct? Check with scope or logic analyzer for activity on NCS, CLK, IO0 and then IO1) and verify that CLK speed is within allowed range for the flash.

Tesla DeLorean

Guru

A BSP or an External Loader?

On what STM32, using what pins?

Most BSP should just need to bring up the pins and interface, and get a working READ command in QUAD/32-bit Addressing mode, and then map it.

Got some parts on order from Mouser

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..

Pavel A.Author

Hi Clive,

I'm looking for a driver similar to this but for S25FL512S

Don't laugh - this is my first project with a QSPI flash. STM32H753XIH6 custom board.

I took the BSP example from STM32H743-EVAL2 for the QSPI itself. Initialization of the QSPI seems successful but then I cannot even read the flash ID or status reg without errors in simple 1-line mode.

The flash is connected with all 4 data pins, on bank1. Bank 2 has a QSPI SDRAM (not enabled yet)

Andreas BolschBest answer

Lead III

The S25FL512S is in no way special, a driver for e.g. S25FL128S will work, too (as far as reading status reg., read ID are concerned and even for read for the bottom half).

(The changes for 4-byte address mode are rather simple, e.g. change the command bytes accordingly and the ADSIZE field in QUADSPI_CCR, but that's the final step, when read ID etc. work.)

Probably the pin setup is not correct? Check with scope or logic analyzer for activity on NCS, CLK, IO0 and then IO1) and verify that CLK speed is within allowed range for the flash.

AVI-crak

Senior

https://github.com/AVI-crak/Rtos_cortex/tree/master/qspi_driver

I was too lazy to calculate the sector boundaries, keep the data unchanged, and keep track of all this disgrace.

void qspi_data_wire ( uint8_t* data, uint32_t data_size, uint32_t flash_adres);

Simple writing of data to an arbitrary address. As long as your memory chip is working, there is no point in checking the status. Well, when it breaks, only a soldering iron will help.

Pavel A.Author

That's fantastic ...

AVI-crak

Senior

The full name of the memory chip is W25Q256JV. There are 6 options for the W25Q256xxx series. They differ in body, set of commands, and the number of control registers. You need to find documentation for the full name of your chip, without abbreviations. It is very important!!!

The W25Q256xxx series has shadow registers that load their value from one-time memory. Disposable memory can only be programmed once. For example permanently enable mode 4 data lines. Shadow register writes work in the same way as flash memory writes, the difference is in the speed of completion of the operation.

Shadow registers are not reset by a software reset, just like a hard reset - only by turning off the power. The control registers are loaded from the shadow ones during software and hardware resets, they can also be programmed an unlimited number of times - this is a simple memory with a flash memory interface.

W25Q256xxx will work well if you do not use all the features that the manufacturer has provided. Use only what is required at the moment. Otherwise, it may turn out to be a brick, with a gilded interface for a fixed frequency - for example, to load the firmware of an FPGA chip.

Line of code:

gpio_one_pin(zap_gpio.B.pin02.v_af09_quadspi_clk.speed4.pull_down.lock_on);

My personal bicycle will not work for the stm32h series - there are differences. You will have to replace these lines with your bike (with square wheels).

I'm interested in what you got.

Pavel A.Author

For those who may find this thread in future - ST support answered that the driver for S25FL512S is in the board BSP examples for QSPI - here is one for STM32469I_EVAL:

https://github.com/STMicroelectronics/STM32CubeF4/blob/master/Drivers/BSP/STM32469I_EVAL/stm32469i_eval_qspi.c

This code works with S25FL512S and N25Q512, in fact the commands are defined in the n25q512.h though many register bits differ.

This driver supports only common basic operation of the flash, no specific features of S25FL512S or N25Q512.

To summarize - take the above ...eval_qspi.c file + one or both .h files for S25FL512S and N25Q512 (and as I wrote this should work also with S25FL256S). Then add advanced i/o modes and specific features such as DDR, protections, ECC...

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