2026-01-24 4:33 PM
Hi!
I'm new with STM32CubeIDE and STM32N657X0-Q. I'm working with them because of my bachelor's thesis. My model size es 73KB but 432KB because of activations.
The input of my ML is data generated with CMSIS-DSP but I have issues in LL_ATON_RT_RunEpochBlock() line and, I can't see the output.
I've followed these guidelines:
And I have the following code:
LL_ATON_RT_Init_Network(&NN_Instance_Default); // Initialize passed network instance object
do {
/* Execute first/next step */
ll_aton_rt_ret = LL_ATON_RT_RunEpochBlock(&NN_Instance_Default);
/* Wait for next event */
if (ll_aton_rt_ret == LL_ATON_RT_WFE) {
timeout++;
if (timeout > 1000000)
{
printf("STUCK IN WFE\n\r");
break;
}
//LL_ATON_OSAL_WFE();
}
} while (ll_aton_rt_ret != LL_ATON_RT_DONE);The strange part:
The timeout counter never increments because ll_aton_rt_ret == LL_ATON_RT_WFE is never true. It seems like the NPU isn't generating the expected interrupt or the runtime isn't receiving it.
My questions:
Has anyone else experienced this specific issue where LL_ATON_RT_RunEpochBlock() doesn't return WFE?
Could this be related to CACHEAXI initialization? I've seen mentions of this in other threads. But I don't know how to correct this issue, since I don't have enough experience.
Are there specific steps I'm missing in the NPU initialization sequence?
Any guidance would be greatly appreciated. I feel like I'm close but stuck on this final hurdle!
Thanks in advance for your help.
Tags: stm32n6, nucleo-n657x0q, x-cube-ai, npu, ll_aton, inference, wfe, threadx
2026-01-27 7:58 AM
Hello, I have the exact same issue, have you found a solution yet?
Thanks
2026-01-28 8:14 AM
Hello, have you enabled AXISRAM3, 4, 5 and 6? Enable RAMCFG in CubeMX and edit MX_RAMCFG_Init fuction in main.c:
/**
* @brief RAMCFG Initialization Function
* @PAram None
* @retval None
*/
static void MX_RAMCFG_Init(void)
{
/* USER CODE BEGIN RAMCFG_Init 0 */
/* USER CODE END RAMCFG_Init 0 */
/* USER CODE BEGIN RAMCFG_Init 1 */
/* Enable RAMCFG peripheral clock (must be enabled before accessing RAMCFG registers) */
__HAL_RCC_RAMCFG_CLK_ENABLE();
/* Enable NPU dedicated AXISRAM banks 3, 4, 5, 6 */
__HAL_RCC_AXISRAM3_MEM_CLK_ENABLE();
__HAL_RCC_AXISRAM4_MEM_CLK_ENABLE();
__HAL_RCC_AXISRAM5_MEM_CLK_ENABLE();
__HAL_RCC_AXISRAM6_MEM_CLK_ENABLE();
/* Power on AXISRAM banks (they are in shutdown by default) */
RAMCFG_HandleTypeDef hramcfg_temp = {0};
hramcfg_temp.Instance = RAMCFG_SRAM3_AXI;
HAL_RAMCFG_EnableAXISRAM(&hramcfg_temp);
hramcfg_temp.Instance = RAMCFG_SRAM4_AXI;
HAL_RAMCFG_EnableAXISRAM(&hramcfg_temp);
hramcfg_temp.Instance = RAMCFG_SRAM5_AXI;
HAL_RAMCFG_EnableAXISRAM(&hramcfg_temp);
hramcfg_temp.Instance = RAMCFG_SRAM6_AXI;
HAL_RAMCFG_EnableAXISRAM(&hramcfg_temp);
/* USER CODE END RAMCFG_Init 1 */
/** Initialize RAMCFG SRAM3
*/
hramcfg_SRAM3.Instance = RAMCFG_SRAM3_AXI;
if (HAL_RAMCFG_Init(&hramcfg_SRAM3) != HAL_OK)
{
Error_Handler();
}
/** Initialize RAMCFG SRAM4
*/
hramcfg_SRAM4.Instance = RAMCFG_SRAM4_AXI;
if (HAL_RAMCFG_Init(&hramcfg_SRAM4) != HAL_OK)
{
Error_Handler();
}
/** Initialize RAMCFG SRAM5
*/
hramcfg_SRAM5.Instance = RAMCFG_SRAM5_AXI;
if (HAL_RAMCFG_Init(&hramcfg_SRAM5) != HAL_OK)
{
Error_Handler();
}
/** Initialize RAMCFG SRAM6
*/
hramcfg_SRAM6.Instance = RAMCFG_SRAM6_AXI;
if (HAL_RAMCFG_Init(&hramcfg_SRAM6) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN RAMCFG_Init 2 */
/* USER CODE END RAMCFG_Init 2 */
}this solved my issue.