Specifically for the SPC58 -- although it looks like the 56/57 share the same registers. I've reviewed the documentation for the time base registers (TBU/TBL) and have made an attempt to enable it. Leaving the timebase clock (SEL_TBCLK) at the processor clock the documentation indicates I should enable the timebase by writing 0x1 to HID0[TBEN].
I've applied the the required syncronization before and after the mtspr instruction (HID is SPR 1008). HID0[TBEN] continues to indicate it is not enabled and the TBL/TBU registers are inaccessible. I can toggle on the ICR bit (or many others in the HID0 register), but TBEN continues to elude me.
What basic requirement am I missing?
Thanks
